3D Memory Chip Block Testing for Stacking Defect Analysis
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Solution Overview
Problem
The complexity of packaging and stacking in three-dimensional memory chips often leads to a large number of additional failed memory cells, making it difficult to analyze failure causes effectively.
Innovation Solution
A testing method and system that divides memory chips into blocks, detects failed signal lines and memory cells, sets thresholds, and determines distribution patterns of failed memory cells to simplify analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory chips use complex packaging and stacking, then memory capacity and integration are improved, but the number of failed memory cells increases and failure analysis becomes difficult
Solution Approach 1:
The patent divides each memory chip into multiple memory blocks, and further segments the analysis by categorizing failed memory cells into different distribution patterns (first, second, and third patterns). This segmentation allows the system to handle complex failure data by breaking it down into manageable, analyzable units with distinct characteristics.
Solution Approach 2:
The patent introduces a new dimension of analysis by classifying failed memory cell distributions into multiple patterns based on their spatial arrangements. Instead of treating all failed cells uniformly, the system adds a classification dimension that distinguishes between different failure modes, enabling more effective failure cause identification despite the complexity of three-dimensional stacking.
2Quantity of substance
If three-dimensional memory chips use complex packaging and stacking, then memory capacity is improved, but failure cause analysis becomes difficult
Solution Approach 1:
The patent segments the failure analysis process into distinct steps: detecting failed memory cells, determining their distribution patterns, and analyzing causes based on pattern categories. This segmentation transforms a complex, monolithic analysis problem into a systematic multi-step process that is easier to execute and interpret.
Solution Approach 2:
The patent changes the parameter of failure representation from raw failed cell locations to categorized distribution patterns. By transforming the data into pattern-based parameters (first pattern, second pattern, third pattern), the system simplifies the complexity of failure analysis while retaining all necessary information for cause determination.
3Measurement precision
If all failed memory cells are detected and analyzed in detail, then measurement precision is improved, but device complexity and analysis time increase
Solution Approach 1:
The patent merges multiple failed memory cells that share the same distribution pattern into a single analytical category. Instead of analyzing each failed cell individually, the system combines them by pattern type, reducing the overall complexity while maintaining measurement precision through pattern-based characterization.
Solution Approach 2:
The patent transforms the analysis from individual cell-level parameters to pattern-level parameters. By changing the parameter representation from discrete failed cell coordinates to aggregated distribution patterns, the system reduces data complexity while preserving the essential information needed for precise failure cause identification.
Data Source
AI summary
Disclosed are a testing method and a testing system. The testing method is configured to scan a three-dimensional memory chip. The three-dimensional memory chip includes a plurality of memory chips stacked with each other. The testing method includes: dividing each memory chip into a plurality of memory blocks; testing each memory block to detect a total failed first signal line quantity from a plurality of first signal lines extending along a first direction in each memory block, and to detect a total failed memory cell quantity of each memory block; and determining a failed bit quantity threshold according to the total failed first signal line quantity, and comparing the total failed memory cell quantity with the failed bit quantity threshold, to accordingly determine whether to set a marked first signal line quantity.