3D Memory Cell Structure With Blocking Spacers for Lower Parasitic Capacitance
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Solution Overview
Problem
The challenge of increasing memory cell density and reducing parasitic capacitance in semiconductor devices is hindered by structural limitations, particularly in three-dimensional memory cells.
Innovation Solution
A semiconductor device with vertically stacked memory cells, including a word line stack, vertically extending blocking spacers, and storage nodes of a capacitor, supported by supporters, is fabricated using a method that involves forming alternating stacks, etching openings, and replacing sacrificial layers with word lines and bit lines, with silicon carbon oxide used for blocking spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cell size is reduced continuously to increase net die, then memory cell density is improved, but parasitic capacitance increases and structural limitations are encountered
Solution Approach 1:
The patent transitions from planar memory cell arrangement to three-dimensional vertical stacking. Multiple memory cells are stacked vertically along the z-axis, with word lines extending vertically through multiple layers. This dimensional change allows increased memory cell density without proportionally increasing parasitic capacitance, as vertical stacking separates capacitance paths more effectively than lateral scaling alone.
Solution Approach 2:
The patent segments the memory cell structure into distinct functional layers with isolation layers positioned between adjacent memory cells. These isolation layers electrically separate the memory cells, reducing parasitic capacitance coupling between them while maintaining high density through vertical integration.
2Productivity
If three-dimensional memory cell structure is implemented to increase net die, then memory cell density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs sacrificial layers formed in advance during the fabrication process. These sacrificial layers are deposited before final structure formation, serve as temporary placeholders or etch stop layers, and are subsequently removed or replaced. This preliminary action simplifies the overall manufacturing process by breaking down complex 3D fabrication into sequential, manageable steps.
Solution Approach 2:
The patent introduces isolation layers as intermediary structures between adjacent memory cells. These isolation layers serve as mediators that provide electrical isolation, mechanical support, and process definition, thereby reducing the direct complexity of fabricating closely spaced 3D memory cells by providing intermediate structural elements.
Data Source
AI summary
A semiconductor device may include a word line stack over a substrate; a plurality of supporters including vertically extending blocking spacers to support the word line stack; and storage nodes of a capacitor disposed laterally between the supporters.