3D Memory Stack With Schottky Active Body for Body Erase
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Solution Overview
Problem
Conventional microelectronic device configurations, particularly in memory devices, face challenges in reducing size and improving performance due to processing conditions and design limitations, which impede increased integration density, faster memory cell switching, lower power consumption, and faster data transfer rates.
Innovation Solution
The solution involves forming a microelectronic device structure with a stack structure comprising vertically alternating conductive and insulative tiers, cell pillar structures extending through the stack, and an active body with a high work function metal material for Schottky contacts, allowing for body erase operations and integrating control logic devices for efficient memory cell control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional memory device configurations are used, then manufacturing processes are established, but integration density cannot be increased and device size cannot be reduced
Solution Approach 1:
The patent transitions from planar two-dimensional memory arrays to three-dimensional vertical memory arrays. Memory strings extend vertically through multiple decks stacked above the control logic region, enabling increased integration density by utilizing the vertical dimension rather than expanding horizontally. This dimensional change allows more memory cells to be packed into the same die area.
Solution Approach 2:
The memory device is divided into distinct functional regions: a control logic region and a memory array region. The memory array is further segmented into multiple decks, each containing tiers of conductive structures and dielectric materials, with vertical memory strings extending through openings in these decks. This segmentation allows independent optimization of control logic and memory storage functions.
2Reliability
If processing conditions are optimized for memory array formation, then memory array performance improves, but control logic device configurations and performance are limited
Solution Approach 1:
The device is segmented into a control logic region and a memory array region that can be formed independently. This allows separate optimization of processing conditions for each region - the control logic region can use standard CMOS processing while the memory array region uses specialized processes for forming vertical memory strings, charge trapping layers, and tunnel dielectrics.
Solution Approach 2:
An isolation structure is introduced as an intermediary between the control logic region and the memory array region. This isolation structure enables independent formation and processing of the two regions, allowing the memory array to be formed over the control logic region without interfering with control logic device operation or limiting control logic design flexibility.
3Quantity of substance
If conventional planar arrangements are used, then manufacturing is simpler, but fewer switching devices can be located in a unit of die area
Solution Approach 1:
The patent implements a three-dimensional vertical memory array architecture where memory strings extend vertically through multiple decks. Each vertical memory string contains multiple memory cells formed by intersections with bit lines and word lines. This vertical stacking enables a greater number of switching devices to be located in a unit of die area compared to conventional planar arrangements, as memory cells are distributed across multiple vertical levels rather than spread out horizontally.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances memory device performance by enabling body erase operations with relaxed current margins, reduced trapping, and eliminating the need for epitaxial material, while allowing for compact design and efficient control logic integration.
Implementation Method 1
an active body with a high work function metal material for Schottky contacts
Implementation Method 2
body erase operations with relaxed current margins
Data Source
AI summary
A microelectronic device comprises a stack structure, cell pillar structures, an active body structure, digit line structures, and control logic devices. The stack structure comprises vertically neighboring tiers, each of the vertically neighboring tiers comprising a conductive structure and an insulative structure vertically neighboring the conductive structure. The cell pillar structures vertically extend through the stack structure and each comprise a channel material and an outer material stack horizontally interposed between the channel material and the stack structure. The active body structure vertically overlies the stack structure and is in contact with the channel material of the cell pillar structures. The active body structure comprises a metal material having a work function greater than or equal to about 4.7 electronvolts. The digit line structures vertically underlie the stack structure and are coupled to the cell pillar structures. Memory devices, electronic systems, and methods of forming a microelectronic device are also described.