Three-Dimensional Memory Bonded Chip Assembly With Through-Substrate Via Structures
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Solution Overview
Problem
The manufacturing of three-dimensional NAND flash memory devices faces challenges in reducing memory opening pitch and increasing word line density, leading to complexity in etch and metal replacement processes, and the thermal budget used in CMOS processes affects CMOS device performance, particularly for CMOS-under-array peripheral circuits.
Innovation Solution
The solution involves forming through-substrate via structures in a replacement-scheme process integration, where CMOS and memory chips are separately fabricated and bonded using surface-activated bonding, allowing for independent thermal processing and reducing thermal budget constraints, and forming integrated through-substrate via and pad structures with tubular insulating spacers and metallic materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the pitch of memory openings is reduced and the number of word lines is increased to achieve high density, then storage capacity is improved, but the complexity of the etch process and metal replacement process increases
Solution Approach 1:
The patent divides the monolithic three-dimensional NAND memory device into multiple separate semiconductor chips, each containing a portion of the memory array. These chips are then bonded together using through-substrate via structures to form a stacked configuration. This segmentation approach reduces the etch process complexity within each individual chip while achieving high overall storage capacity through the stacked arrangement of multiple chips.
2Quantity of substance
If multi-tier structures are used for three-dimensional NAND memory devices, then storage density is improved, but the complexity in the manufacturing process increases
Solution Approach 1:
The patent implements multi-tier storage by stacking multiple separate semiconductor chips vertically, with each chip forming a tier. The chips are bonded together through through-substrate via structures that penetrate the substrate of each chip. This approach achieves high storage density through the vertical stacking of multiple tiers while simplifying the manufacturing process compared to forming complex multi-tier structures within a single monolithic device.
3Ease of manufacture
If CMOS and memory chips are processed together in the same thermal budget, then integration is simplified, but CMOS device performance is degraded
Solution Approach 1:
The patent separates CMOS peripheral circuits and memory arrays into different semiconductor chips. The CMOS chip is processed with appropriate thermal budget for optimal CMOS device performance, while the memory chip(s) are processed separately with thermal budgets optimized for memory formation. The separately processed chips are then bonded together using through-substrate via structures, achieving both high CMOS performance and effective integration.
4Reliability
If through-substrate via structures are formed with metallic materials, then electrical connectivity is improved, but copper contamination risk increases
Solution Approach 1:
The patent employs tubular insulating spacers as intermediary structures surrounding the metallic via structures. These insulating spacers act as barriers that contain the metallic material within the via structures and prevent copper contamination of the surrounding semiconductor substrate and devices. The insulating spacers maintain electrical isolation while allowing electrical connectivity through the via structures to be established.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, improves wafer chip yield, and minimizes copper contamination while maintaining high thermal budget flexibility, enabling efficient integration of CMOS and memory devices in a bonded structure.
Implementation Method 1
bonded using surface-activated bonding
Data Source
AI summary
Multiple semiconductor chips can be bonded through copper-to-copper bonding. The multiple semiconductor chips include a logic chip and multiple memory chips. The logic chip includes a peripheral circuitry for operation of memory devices within the multiple memory chips. The memory chips can include front side bonding pad structures, backside bonding pad structures, and sets of metal interconnect structures providing electrically conductive paths between pairs of a first side bonding pad structure and a backside bonding pad structure. Thus, electrical control signal can vertically propagate between the logic chip and an overlying memory chip through at least one intermediate memory chip located between them. The backside bonding pad structures can be formed as portions of integrated through-substrate via and pad structures that extend through a respective semiconductor substrate.