3D Memory Interconnection Layout for Reliable Bonded IC Stacks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing integrated circuit devices face challenges in achieving reliable interconnection structures with improved integration and reduced chip size, particularly in memory devices with complex operation circuits and interconnection structures.
Innovation Solution
The integrated circuit device incorporates a memory cell interconnection unit with upper conductive patterns electrically connectable to a memory stack unit, surrounded by memory cell insulation. It also includes a peripheral circuit interconnection unit with lower conductive patterns bonded to the memory cell interconnection unit, featuring conductive bonding structures and through electrodes to enhance electrical connectivity and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory devices are highly integrated with reduced chip size, then integration density is improved, but interconnection reliability deteriorates
Solution Approach 1:
The patent transitions from planar interconnection to three-dimensional vertical interconnection by forming bit lines and word lines that extend in the vertical direction through stacked memory cells. Through-electrodes penetrate multiple insulating layers to establish vertical electrical connections, enabling high-density integration while maintaining signal integrity through controlled impedance pathways.
Solution Approach 2:
The patent implements nested interconnection structures where conductive bonding structures are embedded within insulating layers, which are themselves surrounded by protective insulation. The bit lines and word lines are nested within the vertical stack, with through-electrodes penetrating through multiple nested insulating layers to establish connections between different functional blocks.
2Reliability
If conductive bonding structures are added to improve connectivity, then electrical connection is improved, but resistance increases
Solution Approach 1:
The patent employs composite interconnection structures combining different materials with complementary properties. Copper or aluminum conductive bonding structures are used for low-resistance horizontal connections, while vertical through-electrodes use materials optimized for penetrating insulating layers. The insulating layers themselves are composite structures providing both electrical isolation and mechanical support.
Solution Approach 2:
The patent introduces intermediate conductive layers and bonding structures that mediate between different interconnection levels. These intermediary elements provide transition pathways that maintain low resistance while enabling connections between vertically stacked memory cells and peripheral circuits, acting as electrical bridges across insulating barriers.
3Adaptability or versatility
If peripheral circuits are integrated with memory cells, then device functionality is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the integrated circuit into distinct functional segments: memory cell arrays with vertical bit line/word line stacks, peripheral circuit regions with separate interconnection layers, and insulating layers that physically and electrically separate these segments. This segmentation allows independent optimization and manufacturing of different functional blocks while maintaining overall integration.
Solution Approach 2:
The patent employs universal interconnection structures that serve multiple functions: through-electrodes simultaneously provide electrical connections, define layer boundaries, and enable both memory cell access and peripheral circuit interconnection. The insulating layers provide both electrical isolation and structural support for multiple functional blocks, reducing the need for separate specialized structures.
Data Source
AI summary
An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.