3D Memory Structure With Bonded Logic Layers for Shorter Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scaling of Integrated Circuits (ICs) has led to performance and memory capacity stalls due to wire degradation and high energy costs in memory fetches, necessitating innovative approaches for 3D semiconductor devices to enhance memory capacity and performance without increasing production costs.
Innovation Solution
A 3D semiconductor device architecture featuring single crystal transistors with oxide-to-oxide bonds, where a first level comprising processors is overlaid by a second level with memory cells, achieving high-density NOR memory with reduced wire lengths and improved integration of logic and memory through advanced fabrication methods such as layer transfer and bonding techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If component sizes are reduced through scaling, then transistor density and performance improve, but wire performance degrades and energy consumption increases
Solution Approach 1:
The patent transitions from 2D planar integration to 3D vertical stacking, arranging transistors and wires across multiple levels. This dimensional change allows transistors to be placed closer in the vertical dimension while keeping wire lengths manageable, thereby maintaining high transistor density without proportionally increasing wire length and energy consumption
2Productivity
If component sizes are reduced through scaling, then transistor density improves, but wire length increases causing performance degradation
Solution Approach 1:
By stacking multiple transistor layers vertically, the patent reduces the lateral distance between connected transistors. Wires can be routed within the same layer or between adjacent layers, significantly shortening wire lengths compared to 2D layouts where all connections must occur on the same plane
Solution Approach 2:
The patent implements a hierarchical structure where multiple levels of transistors and wires are nested vertically. Each level contains complete functional units, and levels are interconnected through vertical vias, creating a compact nested architecture that reduces overall wire length while maintaining high density
3Speed
If 3D stacking is implemented, then wire lengths are reduced and performance improves, but manufacturing complexity increases
Solution Approach 1:
The patent divides the 3D structure into repeating modular units, each containing transistors and wires arranged in the same pattern. This segmentation allows standardization of fabrication processes for each layer, reducing manufacturing complexity despite the increased 3D complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-speed access and high-density memory with reduced power consumption and latency, effectively addressing the limitations of current IC scaling by integrating logic and memory more efficiently and reducing wire-related performance issues.
Implementation Method 1
said bonded comprises oxide to oxide bonds
Data Source
AI summary
A 3D semiconductor device, the device including: a first level including first single crystal transistors; and a second level including second single crystal transistors, where the first level is overlaid by the second level, where a vertical distance from the first single crystal transistors to the second single crystal transistors is less than eight microns, where the second level includes a layer transferred and bonded level, where the bonded includes oxide to oxide bonds, where the first level includes a plurality of processors, and where the second level includes a plurality of memory cells.