3D Semiconductor Memory Vertical Stacking Integration
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Solution Overview
Problem
Two-dimensional semiconductor memory devices face limitations in performance and manufacturing cost due to interference between memory cells and the need for expensive equipment for fine patterning, while three-dimensional devices aim to increase capacity and performance but struggle with size and integration challenges.
Innovation Solution
A three-dimensional semiconductor memory device is designed with a cell wafer and peripheral wafers bonded in a non-monolithic structure, featuring separate sub-memory cell arrays on both surfaces of the cell wafer, allowing for independent operation and reduced size through vertical stacking and optimized decoder and page buffer circuit layouts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional planar structure is used to store more data, then storage capacity increases, but interference between memory cells becomes severe causing performance degradation
Solution Approach 1:
The patent transitions from a two-dimensional planar structure to a three-dimensional vertical structure by stacking memory cells vertically. The source plate extends in the vertical direction with bit lines extending in first and second directions, creating a立体 architecture that increases storage capacity while reducing cell interference through spatial separation in multiple dimensions.
2Quantity of substance
If fine patterning process is introduced to increase integration, then storage capacity increases, but manufacturing cost increases due to expensive equipment
Solution Approach 1:
The patent achieves high integration through vertical stacking rather than horizontal miniaturization. The source plate and bit lines are configured in three dimensions, allowing increased storage capacity without requiring extreme fine patterning processes, thereby avoiding the need for expensive equipment.
3Quantity of substance
If three-dimensional structure is used to increase capacity, then storage capacity and performance improve, but device size and integration complexity increase
Solution Approach 1:
The patent divides the memory device into distinct functional components: a source plate with vertically extending bit lines, first and second word lines extending in different directions, and separate first and second memory blocks. This segmentation allows for modular integration and simplified manufacturing of the three-dimensional structure.
Solution Approach 2:
The patent implements different structural configurations in different regions: the source plate extends in the vertical direction with bit lines, while first word lines extend in a first direction and second word lines extend in a second direction. This local differentiation optimizes each region's function while managing overall device complexity.
Data Source
AI summary
A three-dimensional semiconductor memory device may include a cell wafer including a source plate, a plurality of first word lines stacked to be spaced apart from one another along a plurality of first vertical channels projecting from a bottom surface of the source plate in a vertical direction, and a plurality of second word lines stacked to be spaced apart from one another along a plurality of second vertical channels projecting from a top surface of the source plate in a vertical direction; a first peripheral wafer bonded to a bottom surface of the cell wafer, and including a first row decoder unit which transfers an operating voltage to the plurality of first word lines; and a second peripheral wafer bonded to a top surface of the cell wafer, and including a second row decoder unit which transfers an operating voltage to the plurality of second word lines.