3D Memory Array Bonding for Compact DRAM Control Logic
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Solution Overview
Problem
Microelectronic device designers face challenges in reducing the size and improving the performance of memory devices, such as DRAM devices, due to processing conditions and the configuration of control logic devices, which limit the reduction of feature dimensions and performance enhancements like faster speed and lower power consumption.
Innovation Solution
The method involves forming microelectronic devices with array regions, digit line exit regions, word line exit regions, and socket regions, using conductive and insulative materials, and specific structures like contact structures and routing tiers to facilitate electrical connections and optimize the arrangement of control logic devices, allowing for more compact and high-performance designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If control logic devices are provided in electrical communication with digit lines and word lines by way of routing and contact structures, then the memory array can be controlled, but the processing conditions (temperatures, pressures, materials) limit the configurations and performance of the control logic devices
Solution Approach 1:
The device is divided into a memory array region and a control logic region that are physically separated and formed at different processing stages. The control logic devices are formed in a separate region that is not subjected to the same high-temperature processing as the memory array, allowing independent optimization of each region's processing conditions and device configurations.
Solution Approach 2:
The control logic devices are extracted from the memory array region and placed in a separate control logic region. This separation removes the constraint where control logic devices had to withstand the same processing conditions as the memory array, enabling greater design flexibility and performance optimization.
2Reliability
If the quantities, dimensions, and arrangements of control logic devices are increased to improve control functionality, then the memory array can be better controlled, but the horizontal footprint of the memory device increases
Solution Approach 1:
The control logic devices are arranged in a vertical stack configuration rather than a planar layout. Multiple control logic devices are stacked vertically above each other, allowing increased control functionality without proportionally increasing the horizontal footprint. This vertical integration reduces the area occupied by control logic while maintaining or enhancing control capabilities.
3Productivity
If feature dimensions are reduced to increase integration density, then more features can be packed into the device, but processing conditions limit the minimum achievable feature dimensions
Solution Approach 1:
The fabrication process is segmented into distinct stages: first forming the memory array with its specific processing conditions, then forming the control logic devices in a separate region with different, optimized processing conditions. This allows each region to achieve its optimal feature dimensions and integration density without being constrained by the processing requirements of the other region.
Data Source
AI summary
A method of forming a microelectronic device comprises forming a microelectronic device structure assembly comprising memory cells, digit lines coupled to the memory cells, word lines coupled to the memory cells, and isolation material overlying the memory cells, the digit lines, and the word lines. An additional microelectronic device structure assembly comprising control logic devices and additional isolation material overlying the control logic devices is formed. The additional isolation material of the additional microelectronic device structure assembly is bonded to the isolation material of the microelectronic device structure assembly to attach the additional microelectronic device structure assembly to the microelectronic device structure assembly. The memory cells are electrically connected to at least some of the control logic devices after bonding the additional isolation material to the isolation material. Microelectronic devices, electronic systems, and additional methods are also described.