3D Memory Cell Array Bonding Structure for Easier Semiconductor Fabrication
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Solution Overview
Problem
The manufacturing process of three-dimensional semiconductor devices is complex and poses challenges in terms of integration density and process difficulty.
Innovation Solution
The semiconductor device incorporates a memory cell array with a first stack structure comprising alternating interlayer insulating layers and conductive patterns, separated by a bonding structure, and includes vertical channels and separation insulating layers to simplify the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in three dimensions on a substrate, then integration density is improved, but manufacturing process complexity increases
Solution Approach 1:
The memory cell array is divided into multiple sub-memory cell arrays (first sub-memory cell array, second sub-memory cell array, etc.) that are disposed at different heights above the substrate. Each sub-memory cell array is further segmented into stack structures with alternating conductive patterns and interlayer insulating layers. This segmentation allows the complex three-dimensional structure to be manufactured in manageable sections rather than as a single monolithic unit.
Solution Approach 2:
The patent transitions from planar two-dimensional memory cell arrangement to three-dimensional vertical stacking. Memory cells are arranged not only horizontally on the substrate but also vertically at different heights, creating multiple layers of memory cells stacked above each other. This dimensional change dramatically increases integration density while the bonding structure methodology manages the resulting manufacturing complexity.
2Ease of manufacture
If bonding structures are used to connect sub-memory cell arrays, then manufacturing process difficulty is reduced, but device structure complexity increases
Solution Approach 1:
The bonding structure is segmented into multiple functional components: bonding insulating layers, bonding conductive patterns, and separation insulating layers. Each component performs a specific function - the bonding insulating layers provide electrical isolation, the bonding conductive patterns establish electrical connections between sub-memory cell arrays, and the separation insulating layers distinguish adjacent memory cell arrays. This segmentation simplifies the manufacturing process by allowing each component to be formed through specialized processes.
Solution Approach 2:
The bonding structure acts as an intermediary element between sub-memory cell arrays, facilitating their connection while managing electrical signals and power. The bonding conductive patterns serve as intermediary conductors that transfer signals between different height levels, while bonding insulating layers provide intermediary isolation to prevent unwanted electrical interference. This intermediary approach reduces manufacturing difficulty by creating standardized connection interfaces.
Data Source
AI summary
A semiconductor device includes a peripheral circuit structure, a memory cell array disposed over the peripheral circuit structure, and a bonding structure disposed between the peripheral circuit structure and the memory cell array. The memory cell array includes a first stack structure including first interlayer insulating layers and first conductive patterns disposed alternately with each other in a first direction over the bonding structure, second conductive patterns separated from each other in a horizontal direction between the first stack structure and the bonding structure, each of the second conductive patterns comprising electrode portions spaced apart from in the first direction and a connection portion extending in the first direction to couple the electrode portions, a vertical channel passing through the first stack structure and the electrode portions of each of the second conductive patterns, and a separation insulating layer disposed between the second conductive patterns.