3D Memory Bonding Structure With Vertical Conductive Isolation
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Solution Overview
Problem
Current semiconductor devices face challenges in enhancing data storage capacity and electrical properties while maintaining reliability, particularly in three-dimensional memory cell arrangements.
Innovation Solution
The semiconductor device incorporates a stacked structure with gate electrodes, channel structures, and an isolation structure that includes a vertical conductive layer, integrated with a plate conductive layer, to improve electrical connectivity and reliability, using materials like tungsten, copper, or aluminum for enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally to increase data storage capacity, then storage capacity is improved, but electrical properties and reliability may deteriorate
Solution Approach 1:
The device is divided into two separate semiconductor structures (first and second structures) that are bonded together. The first structure contains circuit devices and lower wiring, while the second structure contains the stacked gate electrodes and channel structures. This segmentation allows independent optimization of each structure's electrical properties while achieving high storage capacity through the three-dimensional arrangement in the bonded configuration.
Solution Approach 2:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional stacking by stacking multiple gate electrodes vertically in the second semiconductor structure. This dimensional change increases data storage capacity while the separate bonding structure maintains electrical reliability by providing dedicated wiring paths and isolation between layers.
2Quantity of substance
If three-dimensional memory cell arrangement is implemented to increase storage capacity, then storage capacity is improved, but electrical connectivity may worsen
Solution Approach 1:
The patent introduces bonding structures (lower bonding structure and upper bonding structure) as intermediaries to establish electrical connectivity between the first and second semiconductor structures. These bonding structures serve as mediator layers that facilitate reliable electrical connections while allowing the three-dimensional stacking configuration to increase storage capacity.
Solution Approach 2:
The patent replaces complex three-dimensional wiring mechanisms with a bonded structure approach. Instead of attempting to route wires through the three-dimensional memory cell array, the invention uses separate bonded semiconductor structures with dedicated wiring layers, substituting a mechanically simpler bonding interface for complex electrical routing.
3Quantity of substance
If stacked gate electrode structure is used to increase storage capacity, then storage capacity is improved, but manufacturing complexity increases
Solution Approach 1:
The complex stacked gate electrode structure is segmented into two separate semiconductor structures that are manufactured independently and then bonded together. This segmentation simplifies the manufacturing process by allowing each structure to be fabricated using standard processes, avoiding the need to manufacture the entire stacked configuration in a single complex process.
Solution Approach 2:
Each semiconductor structure is designed to be self-contained and self-serviceable, with the first structure containing its own circuit devices and wiring, and the second structure containing its own stacked gate electrodes and channel structures. This self-service design allows independent manufacturing and testing of each structure before bonding, reducing overall manufacturing complexity.
Data Source
AI summary
A semiconductor device includes a first semiconductor structure including a lower bonding structure, and a second semiconductor structure including a second substrate disposed on the first semiconductor structure, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to a lower surface of the second substrate, an upper bonding structure bonded to the lower bonding structure, a plate conductive layer disposed on an upper surface of the second substrate, electrically connected to a channel layer, and including a metal material, and an isolation structure penetrating an entirety of the gate electrodes and extending in a second direction perpendicular to the first direction. The isolation structure includes a vertical conductive layer that extends from and is integrated with the plate conductive layer, and that includes a same metal material as the metal material of the plate conductive layer.