3D Memory Wafer Bonding Layout for Balanced Word Line Loads
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Solution Overview
Problem
Existing 3D memory architectures face issues with unbalanced loads at the ends of word lines during bonding, leading to abnormal bonding and metal voids due to electrochemical reactions, resulting in packaging failures and economic losses.
Innovation Solution
A balanced load configuration is implemented at the two ends of the test structure by connecting both ends symmetrically to test pins via peripheral wafer jumpers, ensuring equal circuit arrangements and reducing the impact of electroplating reactions during bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If word line ends are connected asymmetrically to bonding contacts, then bonding process is simpler, but electrochemical reactions cause metal voids and bonding failures
Solution Approach 1:
The patent applies asymmetry in reverse - it creates a symmetric configuration to resolve an asymmetric problem. The word line ends are connected to bonding contacts through equal numbers of contact blocks (e.g., two contact blocks at each end), creating symmetric circuit arrangements that balance electrochemical reactions during bonding, thereby preventing metal voids while maintaining manufacturing feasibility
Solution Approach 2:
The patent creates equipotential conditions by ensuring both ends of the word line have equal circuit arrangements with the same number of contact blocks and similar path lengths to bonding contacts. This balancing equalizes electrochemical potentials during bonding, preventing the electrochemical reactions that cause metal voids in asymmetric configurations
2Device complexity
If unbalanced load configuration is used at word line ends, then circuit design is simpler, but electroplating reactions during bonding increase metal void formation
Solution Approach 1:
The patent uses symmetric configuration (opposite of asymmetry principle) to balance the circuit arrangements at both word line ends, ensuring equal numbers of contact blocks and similar path lengths, which eliminates the unbalanced load that causes electroplating reactions and metal void formation during bonding
Solution Approach 2:
The patent changes the circuit parameters (number of contact blocks, path length) at the word line ends to be equal, transforming the unbalanced configuration into a balanced one. This parameter adjustment equalizes the electrochemical conditions during bonding, preventing metal void formation while maintaining reasonable circuit design complexity
3Reliability
If symmetric circuit arrangements are implemented at both ends of test structure, then bonding reliability improves, but device complexity increases
Solution Approach 1:
The patent implements a universal configuration where both ends of the test structure use identical circuit arrangements with the same number of contact blocks and similar path lengths. This symmetric design serves multiple functions: it balances electrochemical reactions, prevents metal voids, and provides manufacturing robustness, thereby improving bonding reliability without excessive complexity increase
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces metal void formation, enhancing bonding reliability and minimizing packaging failures, thereby improving the yield and reducing economic losses.
Implementation Method 1
After the two wafers have been prepared, they can be bonded together such that the bonded array wafer and peripheral wafer are connected to each other through corresponding bonding contacts
Implementation Method 2
leading to abnormal bonding and metal voids due to electrochemical reactions
Data Source
AI summary
The present disclosure discloses a three-dimensional (3D) memory, which includes a peripheral wafer and an array wafer. The peripheral wafer includes a first peripheral structure and a second peripheral structure. The array wafer includes a substrate, a structure to be tested and multiple interconnecting portions. The substrate includes a first well region and a second well region. The array wafer includes the structure to be tested which has a first connecting portion, a second connecting portion, and multiple interconnecting portions. The first peripheral structure is connected to the first well region and the first connecting portion of the structure to be tested by the first interconnecting portion and the second interconnecting portion respectively. The second peripheral structure is connected to the second well region and the second connecting portion of the structure to be tested by the third interconnecting portion and the fourth interconnecting portion respectively.