3D Memory Stack Bonding and Insulation Against Leakage
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity while maintaining reliability and preventing defects such as short-circuits and leakage currents.
Innovation Solution
A semiconductor device design featuring a stacked structure with gate electrodes, channel structures, and insulating regions that include inclined side surfaces to enhance connectivity and reduce defects, utilizing copper for bonding and dielectric materials for insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensionally arranged memory cells are used to increase data storage capacity, then storage density is improved, but manufacturing precision and reliability deteriorate due to increased complexity
Solution Approach 1:
The semiconductor device is divided into a first substrate structure and a second substrate structure that are bonded together. The second substrate structure contains the three-dimensionally arranged memory cells with gate electrodes, channel structures, and insulating regions. This segmentation allows the complex 3D structure to be manufactured and tested separately before final assembly, improving manufacturing precision and reliability.
Solution Approach 2:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple gate electrodes are stacked in the first direction perpendicular to the plate layer, with channel structures penetrating through them. This vertical stacking increases storage capacity by utilizing the third dimension while maintaining manufacturability through the bonded substrate structure.
2Quantity of substance
If three-dimensionally arranged memory cells are used to increase data storage capacity, then storage density is improved, but device reliability deteriorates due to potential defects
Solution Approach 1:
An insulating region is provided between adjacent channel structures, extending from an upper surface of the plate layer and penetrating through the plate layer and gate electrodes. This insulating region acts as a preventive measure against short-circuits and leakage currents between adjacent memory cells, ensuring reliable operation of the high-density 3D structure.
Solution Approach 2:
The insulating region serves as an intermediary element between adjacent channel structures. It physically separates the channel structures and prevents electrical interference, thereby maintaining device reliability in the high-density three-dimensional configuration.
3Quantity of substance
If complex stacked structures with multiple gate electrodes are used, then data storage capacity is improved, but device complexity increases
Solution Approach 1:
The device is segmented into two separate substrate structures that are bonded together. The second substrate structure contains the complex stacked arrangement of gate electrodes and channel structures. This segmentation simplifies the manufacturing process by allowing the complex structure to be built and tested independently before final assembly.
Solution Approach 2:
The patent utilizes vertical stacking in the first direction to create multiple gate electrodes and channel structures. This three-dimensional arrangement increases storage capacity without requiring proportional increases in planar area, thereby managing device complexity more effectively.
Data Source
AI summary
A semiconductor device includes a first substrate structure including a substrate, circuit elements, and first bonding metal layers, and a second substrate structure connected to the first substrate structure. The second substrate structure includes a plate layer, gate electrodes stacked in a first direction below the plate layer, separation regions penetrating through the gate electrodes and extending in a second direction and spaced apart from each other in the second direction, an insulating region extending from an upper surface of the plate layer and penetrating through the plate layer and at least one of the gate electrodes between the separation regions, and second bonding metal layers connected to the first bonding metal layers. The insulating region has inclined side surfaces such that a width of the insulating region decreases in a direction toward the first substrate structure.