3D Memory Cell Array Bonding to Protect Peripheral Transistors
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Solution Overview
Problem
Two-dimensional semiconductor devices face limitations in integration due to expensive processing equipment required for fine pattern formation, which hinders the increase in memory cell density and manufacturing cost, prompting the need for three-dimensional semiconductor memory devices with improved reliability and electrical properties.
Innovation Solution
A three-dimensional semiconductor memory device is designed with a peripheral circuit structure and a cell array structure bonded through bonding pads, featuring a stack structure with interlayer dielectric layers and conductive patterns, vertical channel structures, and connection vias, allowing for increased cell capacity and improved reliability by separating the manufacturing processes to avoid damage from heat treatment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor devices are highly integrated to increase memory cell density, then data storage capacity is improved, but manufacturing cost increases due to expensive processing equipment required for fine pattern formation
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked in the vertical direction, allowing significant increase in memory cell density without requiring finer lateral patterning. This dimensional change avoids the need for expensive ultra-fine lithography equipment while achieving high integration.
Solution Approach 2:
The memory device is divided into multiple stacked layers, with each layer containing memory cell transistors and associated wiring. This segmentation into discrete stackable layers allows for modular manufacturing and assembly, reducing overall manufacturing complexity and cost compared to creating extremely fine patterns in a single plane.
2Reliability
If heat treatment is applied during manufacturing to improve electrical properties, then device performance is improved, but peripheral transistors may be damaged
Solution Approach 1:
The device is segmented into a memory cell array region and a peripheral circuit region. Heat treatment processes can be selectively applied to the memory cell region without affecting the peripheral transistors, as they are spatially separated. This allows optimization of electrical properties in the memory region while preserving the peripheral circuits.
Solution Approach 2:
Different thermal processing conditions can be applied to different regions of the device. The memory cell region receives heat treatment to improve its electrical properties, while the peripheral circuit region is protected from such treatment to avoid damage. This localized approach to thermal processing resolves the contradiction between improving reliability and avoiding harm.
3Quantity of substance
If three-dimensional stacked structure is implemented to increase cell capacity, then integration density is improved, but device complexity increases
Solution Approach 1:
The three-dimensional structure is segmented into multiple identical or similar layers that can be manufactured using the same process steps. Each layer contains memory cell transistors, word lines, and bit lines arranged in a consistent pattern. This modular segmentation reduces fabrication complexity compared to creating a monolithic complex structure, as the same processes are repeated for each layer.
Solution Approach 2:
By moving to three-dimensional stacking, the patent achieves high cell capacity per unit area without proportionally increasing lateral device complexity. The vertical stacking allows multiple cells to share common source lines and bit lines, reducing the number of lateral interconnects required and managing complexity effectively.
Data Source
AI summary
Disclosed are 3D semiconductor memory devices and electronic systems including the same. The 3D semiconductor memory device comprises a first substrate, a peripheral circuit structure on the first substrate, and a cell array structure on the peripheral circuit structure. The cell array structure includes a second substrate, a stack structure between the second substrate and the peripheral circuit structure and including interlayer dielectric layers and conductive patterns that are stacked alternately with the interlayer dielectric layers, vertical channel structures that include respective portions the stack structure and include vertical semiconductor patterns, respectively, and connection vias that include respective portions the second substrate and are connected to respective top surfaces of the vertical semiconductor patterns.