3D Memory Bonding Structure for High-Aspect Contact Integration
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Solution Overview
Problem
The integration degree of two-dimensional memory devices is limited by the area occupied by unit memory cells and the requirement for expensive fine pattern forming technology, while three-dimensional memory devices face challenges in high aspect ratio contact etching processes that hinder further integration.
Innovation Solution
An integrated circuit device with a bonding structure of a vertical memory device, where the cell contact plugs penetrate through gate electrodes in a vertical direction, and a node separation structure is used to minimize process margins, allowing the vertical memory device and peripheral circuit structure to be bonded, thereby increasing integration and economic feasibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a vertical memory device with high aspect ratio contact etching is used to increase integration, then the integration degree improves, but the manufacturing complexity and process difficulty increase
Solution Approach 1:
The patent divides the memory device into separate structures: a vertical memory device structure and a peripheral circuit structure, which are formed independently and then bonded together. This segmentation allows each structure to be optimized separately, reducing the overall process complexity while maintaining high integration degree.
Solution Approach 2:
The patent transitions from a planar 2D integration approach to a 3D vertical integration approach by stacking the memory device structure and peripheral circuit structure in the vertical direction. This dimensional change enables higher integration without increasing lateral footprint or process complexity.
2Reliability
If larger landing pads are used to ensure contact reliability, then contact reliability improves, but the area occupied by unit memory cells increases
Solution Approach 1:
The patent separates the contact structures into cell contact plugs within the vertical memory device and bonding pads on the peripheral circuit structure. This segmentation allows the cell contact plugs to be small and vertically integrated, while bonding pads provide reliable external connections, thus maintaining contact reliability without increasing unit cell area.
Solution Approach 2:
The patent moves the contact function from a lateral 2D plane to a vertical 3D dimension by using cell contact plugs that extend vertically through the memory device structure. This vertical transition enables reliable contact with minimal lateral footprint, reducing the area per unit memory cell while maintaining contact reliability.
3Area of moving object
If fine pattern forming technology is used to reduce unit memory cell area, then the area per unit memory cell decreases, but manufacturing cost increases due to expensive equipment
Solution Approach 1:
The patent divides the device into separately formed structures that are bonded together, allowing standard fabrication processes to be used for each structure independently. This avoids the need for expensive fine pattern forming equipment while achieving high integration through vertical stacking and bonding.
Solution Approach 2:
The patent transitions from lateral miniaturization requiring fine pattern forming to vertical integration using standard processes. By stacking structures in the vertical dimension, the patent achieves high integration without the expensive equipment needed for advanced lateral patterning.
Data Source
AI summary
An integrated circuit device includes a first structure and a second structure stacked on the first structure. The first structure includes a first substrate, a peripheral circuit, and a first bonding pad. The second structure includes a second substrate that includes a first side and a second side, a plurality of gate electrodes disposed on the first side of the second substrate, a first cell contact plug that penetrates a first conductive pad of a first gate electrode, is electrically connected to the first gate electrode, penetrates second gate electrodes disposed above the first gate electrode, and is electrically insulated from the second gate electrodes, a first node separation structure that penetrates the second substrate and surrounds an upper part of the first cell contact plug positioned in the second substrate, and a second bonding pad bonded to the first bonding pad.