3D Memory Devices With Oxide-To-Oxide Bonding And Thermal Isolation
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Solution Overview
Problem
As integrated circuits (ICs) scale down, wire performance and power consumption become dominant issues due to increased wire lengths, despite improved transistor performance and density, necessitating innovative 3D stacking techniques to address these challenges.
Innovation Solution
The method involves constructing 3D IC systems through layer transfer technologies, including oxide-to-oxide and conductor-to-conductor bonding, with thermal isolation layers to manage temperature differences between memory and logic strata, enabling efficient integration of memory and logic circuits while reducing thermal conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If 3D stacking of semiconductor devices is implemented, then wire lengths are reduced and wiring delay is kept low, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent divides the semiconductor device into multiple separate layers (first layer, second layer, third layer) that are stacked vertically. Each layer contains specific circuit components (transistors, interconnects, control circuits) that are independently formed and then integrated through wafer bonding, thereby reducing wire lengths while managing complexity through modular construction
Solution Approach 2:
The patent transitions from traditional 2D planar integration to 3D vertical stacking by arranging multiple functional layers in the vertical dimension. This allows circuits to be placed closer together in three-dimensional space, significantly reducing interconnect lengths and wiring delay while maintaining manufacturability through sequential layer formation and bonding
2Productivity
If multiple memory wafers are stacked with control circuits, then memory density and performance improve, but thermal management becomes more challenging due to heat generation in logic strata
Solution Approach 1:
The patent separates memory circuits and control logic into different physical layers (memory layers in first and second strata, control logic in third stratum). This spatial segmentation allows independent thermal management of each layer, with heat-generating logic separated from sensitive memory arrays, facilitating targeted cooling strategies
Solution Approach 2:
The patent introduces intermediate structures between memory layers and control logic layers that serve as thermal management interfaces. These include bonding interfaces with thermal conductivity considerations and potential thermal vias or heat dissipation structures that mediate heat transfer between strata, enabling controlled thermal flow while maintaining electrical functionality
3Strength
If oxide-to-oxide and conductor-to-conductor bonding is used for wafer integration, then bonding strength and electrical connectivity improve, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary preparation of bonding surfaces on each wafer layer before integration, including oxide layer formation and conductor pad patterning. Alignment marks and registration features are pre-formed on each layer to guide precise registration during bonding, reducing the actual precision demand during the bonding process itself
Solution Approach 2:
The patent uses oxide layers as intermediary bonding surfaces between wafer layers. These oxide layers provide a chemically active, mechanically compliant interface that facilitates strong adhesion between layers. The oxide-to-oxide bonding mechanism acts as an intermediary process that tolerates minor surface variations while achieving robust bonding, reducing the stringency of surface precision requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances IC performance by reducing wire lengths, improving thermal isolation, and managing power consumption, thereby addressing the limitations of scaled-down ICs.
Implementation Method 1
a thermal isolation layer disposed between the logic stratum and the first stratum, where the thermal isolation layer is designed so during the device operation a first temperature of the first stratum is at least 20° C. lower than a second temperature of the logic stratum
Implementation Method 2
where the bonding includes oxide to oxide and conductor to conductor bonding
Implementation Method 3
where the bonding includes oxide to oxide and conductor to conductor bonding
Data Source
AI summary
A semiconductor device, the device including: a first level including control circuits, where the control circuits include a plurality of first transistors and a plurality of metal layers; a memory level disposed on top of the first level, where the memory level includes an array of memory cells, where each of the memory cells include at least one second transistor, where the control circuits control the array of memory cells, where the first level is bonded to the memory level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, and where at least one of the memory cells is disposed directly above at least one of the plurality of metal to metal bonding regions.