3D Memory Bonding Via Structure for Higher Integration
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity and achieving high integration and mass productivity, particularly in three-dimensional memory cell arrangements.
Innovation Solution
The semiconductor device incorporates a stacked substrate structure with bonding metal layers, interconnection lines, and insulating layers, featuring tapered bonding vias and dummy bonding metal layers for enhanced electrical connections and integration, along with a data storage system that includes a controller for managing the semiconductor storage device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensionally arranged memory cells are used instead of two-dimensionally arranged memory cells, then data storage capacity is increased, but device complexity increases
Solution Approach 1:
The patent implements three-dimensionally arranged memory cells by stacking multiple substrate structures vertically, transitioning from two-dimensional to three-dimensional arrangement. This allows increased data storage capacity by utilizing the vertical dimension while maintaining manageable complexity through systematic layering of substrate structures with standardized bonding interfaces and modular organization.
2Productivity
If stacked substrate structure with bonding metal layers and interconnection lines is implemented, then degree of integration is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the integrated structure into multiple discrete substrate structures that can be manufactured and processed separately, then bonded together through standardized bonding metal layers and interconnection lines. This segmentation allows each substrate to be manufactured with standard precision requirements while achieving high overall integration through the stacked configuration.
3Reliability
If tapered bonding vias are used for enhanced electrical connections, then electrical connection reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs tapered bonding vias with gradually changing cross-sectional dimensions to improve electrical connection reliability. The tapered geometry provides better stress distribution and enhanced bonding surface area, improving connection reliability while the gradual transition allows for manageable manufacturing complexity through controlled deposition or etching processes.
Data Source
AI summary
A semiconductor device includes a first substrate structure including a first substrate, circuit devices, first interconnection lines, bonding metal layers on upper surfaces of the first interconnection lines, and a first bonding insulating layer on the upper surfaces of the first interconnection lines and on lateral surfaces of the bonding metal layers, and a second substrate structure on the first substrate structure, and including a second substrate, gate electrodes, channel structures, second interconnection lines, bonding vias connected to the second interconnection lines and the bonding metal layers and having a lateral surface that is inclined such that widths of the bonding vias increase approaching the first substrate structure, and a second bonding insulating layer in contact with at least lower portions of the bonding vias. The bonding metal layers include dummy bonding metal layers not connected to the bonding vias and that contacts the second bonding insulating layer.