3D Memory Vertical Channels with Source-Side Boron Doping
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in achieving sufficient gate-induced drain leakage (GIDL) current for effective cell erase operations due to the lack of a sharp p-n junction at the source-select gate electrode layer.
Innovation Solution
The implementation of source-side boron-doped pockets within vertical semiconductor channels, formed by diffusing boron atoms from p-doped source-level semiconductor layers, creates a sharp p-n junction at the source-select gate electrode layer, enhancing GIDL current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional three-dimensional memory devices are used without source-side boron-doped pockets, then the device structure is simpler, but sufficient GIDL current for effective cell erase operations cannot be achieved
Solution Approach 1:
The patent applies local quality by introducing boron-doped pockets at specific locations within the vertical semiconductor channels (at the source select transistor level) rather than uniformly doping the entire channel. This localized doping creates sharp p-n junctions precisely where needed to generate sufficient GIDL current for erase operations, while maintaining simpler structures in other regions of the device.
Solution Approach 2:
The patent employs preliminary action by forming the boron-doped pockets during the channel formation process itself, before subsequent processing steps. The source-level semiconductor layers are formed with boron doping incorporated, and through thermal processing, boron atoms diffuse to create the pockets in advance, preparing the sharp p-n junctions needed for reliable erase operations before the device is fully assembled.
2Reliability
If source-side boron-doped pockets are implemented to create sharp p-n junctions, then sufficient GIDL current is achieved for effective erase operations, but the manufacturing process becomes more complex
Solution Approach 1:
The patent merges multiple functions into the boron-doped pockets: they serve as both the p-type doping region and the sharp junction formation mechanism. By combining the doping function and junction formation into a single integrated structure formed through diffusion, the manufacturing process achieves the desired electrical characteristics without requiring separate complex processing steps for each function.
Solution Approach 2:
The patent applies self-service by utilizing the natural diffusion properties of boron atoms during thermal processing. The boron-doped source-level semiconductor layers automatically diffuse boron atoms to form pockets with appropriate concentration profiles when subjected to thermal treatment, eliminating the need for precise control of complex doping processes and allowing the material itself to self-organize into the required structure.
3Manufacturing precision
If boron atoms are diffused from source-level semiconductor layers to form pockets, then sharp p-n junctions are created at the source-select gate electrode layer, but precise control of dopant concentration becomes more difficult
Solution Approach 1:
The patent applies parameter changes by controlling the thermal processing conditions (temperature, time, atmosphere) to precisely regulate boron diffusion. By adjusting these parameters, the diffusion process achieves the desired pocket depth and dopant concentration profile, creating sharp p-n junctions with controlled electrical characteristics through well-established semiconductor processing techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the erase operation performance of three-dimensional memory devices by providing sufficient GIDL current, facilitating faster and more efficient cell erase operations.
Implementation Method 1
forming a boron-doped pocket having a net p-type doping within each of the vertical semiconductor channels by the boron atoms that diffuse from the at least one source-level semiconductor layer into a bottom region of each of the vertical semiconductor channels
Data Source
AI summary
A three-dimensional semiconductor device includes source-level material layers including a doped semiconductor source contact layer including boron atoms and n-type dopant atoms, an alternating stack of insulating layers and electrically conductive layers located over the source-level material layers, memory stack structures vertically extending through the alternating stack in which each of the memory stack structures comprises a memory film and a vertical semiconductor channel. Each vertical semiconductor channel includes a first region in which n-type dopants have a higher atomic concentration than boron atoms and a second region overlying the first region that includes boron atoms at a higher atomic concentration than n-type dopant atoms to provide a p-n junction at an interface with the first region. Boron atoms in the source-level p-doped layer and an underlying source-level sacrificial layer that is replaced with an n-doped source contact layer yields a sharp p-n junction at the source-select gate electrode layer.