3D Nonvolatile Memory Programming Sequence for Boundary Cell Reliability
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Solution Overview
Problem
Nonvolatile memory devices with three-dimensional stacks face reliability issues due to low reliability memory cells, leading to decreased capacity and increased data loss when data is written or not written in these cells.
Innovation Solution
The nonvolatile memory device is designed with a memory cell array and peripheral circuit region, where program operations are sequenced to prioritize non-adjacent memory cells over adjacent cells near a boundary, adjusting the order of programming to enhance reliability and prevent capacity reduction by controlling the number of bits written in each cell type.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is written in memory cells of low reliability, then storage capacity is utilized, but data loss probability increases
Solution Approach 1:
The patent applies local quality by differentiating between adjacent memory cells (near boundary) and non-adjacent memory cells (far from boundary). Adjacent memory cells have lower reliability due to boundary effects, so the system writes fewer bits or uses more conservative programming for these cells, while non-adjacent cells can store more bits with higher confidence. This localized differentiation optimizes overall storage capacity while maintaining data reliability.
2Quantity of substance
If program operations are performed on all memory cells, then storage capacity is maximized, but reliability of adjacent memory cells decreases
Solution Approach 1:
The patent implements preliminary action by performing program operations on non-adjacent memory cells first, before programming adjacent memory cells. This sequencing allows the system to establish stable data in more reliable cells first, then handle the less reliable adjacent cells with appropriate precautions. The row decoder and page buffer are configured to complete program operations in this specific sequence, preventing data loss in adjacent cells.
3Productivity
If adjacent memory cells are programmed first, then programming efficiency is improved, but data loss probability increases
Solution Approach 1:
The patent applies inversion by reversing the conventional programming sequence. Instead of programming adjacent memory cells first (which would be more efficient but less reliable), the system programs non-adjacent memory cells first, then proceeds to adjacent cells. This inverted sequence prioritizes data reliability over programming efficiency, accepting a slight performance trade-off to prevent data loss in vulnerable adjacent cells.
4Quantity of substance
If memory cells are arranged in three-dimensional stacks, then storage capacity increases, but reliability of some memory cells decreases
Solution Approach 1:
The patent applies segmentation by dividing the three-dimensional memory cell array into distinct regions: adjacent memory cells near the boundary and non-adjacent memory cells away from the boundary. This segmentation allows the system to apply different programming strategies to different segments. The first conductive materials and first insulating layers surround the first portion, while second conductive materials and second insulating layers surround the second portion, creating structurally distinct segments with different reliability characteristics.
Data Source
AI summary
Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.