3D Memory Channel Structure With Smooth Boundary Diameter Transition
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Solution Overview
Problem
Current semiconductor memory devices face challenges in maintaining optimal current characteristics and withstand voltage due to the narrowing of semiconductor layers at boundaries in three-dimensional memory cell structures, leading to increased resistance and potential deterioration of cell performance.
Innovation Solution
Incorporating a second insulating layer between the first and conductive layers in the stacked structure of the semiconductor memory device, which has a higher etching rate than the inter-layer insulating layer, helps maintain a gentle curvature and uniform film thickness, thereby preventing a sharp decrease in semiconductor layer diameter and reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the semiconductor layer width is reduced to increase integration density, then the integration level is improved, but the resistance increases and current characteristics deteriorate
Solution Approach 1:
The patent applies local quality by creating a tapered semiconductor layer structure where the width varies along the stacking direction. The semiconductor layer has a first width at the lower portion and a second width at the upper portion, with the first width being larger than the second width. This local variation in geometry allows the lower portion to provide lower resistance while the upper portion maintains high integration density, thus resolving the contradiction between integration density and current characteristics.
2Productivity
If the semiconductor layer width varies at the boundary of stacked portions, then the integration level is improved, but the resistance rises and cell reliability deteriorates
Solution Approach 1:
The patent employs curvature by implementing a tapered or rounded transition in the semiconductor layer width at the boundary between stacked portions. Instead of an abrupt step change, the width transitions smoothly from the first width to the second width, creating a curved profile. This smooth transition reduces stress concentration and maintains more uniform resistance characteristics, thereby improving manufacturing precision while preserving high integration level.
3Ease of manufacture
If the film thickness is not uniform at the boundary regions, then the manufacturing process is simplified, but the cell reliability deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-designing the semiconductor layer with a tapered structure that anticipates the boundary region challenges. The width variation is built into the layer structure before subsequent manufacturing steps, ensuring that the boundary regions maintain appropriate film thickness and geometric properties. This preliminary structural design ensures cell reliability is maintained while keeping the overall manufacturing process relatively simple.
Data Source
AI summary
A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; a stacked body having a plurality of first insulating layers and conductive layers stacked alternately on the semiconductor substrate; a columnar semiconductor layer contacting the semiconductor substrate in the stacked body being provided extending in a stacking direction of the stacked body and including a first portion and a second portion which is provided above the first portion; a memory layer provided on a side surface of the columnar semiconductor layer facing the stacked conductive layers and extending, along the columnar semiconductor layer; and a second insulating layer provided between one of the first insulating layer and the conductive layers of the stacked body. The columnar semiconductor layer has a boundary of the first portion and the second portion, the boundary being close to the second insulating layer; and an average value of an outer diameter of the memory layer facing a side surface of the second insulating layer is larger than that of the memory layer facing a side surface of a lowermost layer of the first insulating layers in the second portion.