3D Memory Layer Stack Using Sacrificial Layers Against Buckling
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Solution Overview
Problem
Existing semiconductor memory devices face manufacturing challenges due to deflection and buckling of insulating layers, leading to embedding failures and disconnection of conductive layers, which affect the yield and storage capacity of memory cell arrays.
Innovation Solution
The use of alternating layers of sacrifice layers made of different materials, such as polycrystalline silicon and silicon nitride, supported by insulating layers, during the manufacturing process to form hollow structures that reduce stress and structural defects, allowing for the formation of conductive layers without through-holes and enhancing the structural strength of the memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional manufacturing methods are used without alternating sacrifice layers, then the manufacturing process is simpler, but insulating layers experience deflection and buckling leading to embedding failures
Solution Approach 1:
The patent divides the insulating layer structure into alternating layers of first insulating layers and second insulating layers, with sacrifice layers positioned between them. This segmentation allows differential stress management, where the first insulating layers can deflect without causing buckling, while the second insulating layers remain substantially flat. The sacrifice layers act as stress relief elements that prevent embedding failures in the conductive layers, thereby improving manufacturing yield without significantly complicating the overall manufacturing process.
Solution Approach 2:
The sacrifice layers serve as intermediary elements between the first and second insulating layers. These sacrifice layers are specifically designed to be removed after serving their stress-relief function during manufacturing. They mediate the mechanical stresses between different insulating layers, preventing the transmission of harmful stresses that would cause buckling and embedding failures, thus improving reliability while maintaining structural integrity during the manufacturing process.
2Reliability
If alternating sacrifice layers are used to prevent deflection and buckling, then manufacturing yield improves, but the manufacturing process becomes more complex
Solution Approach 1:
The sacrifice layers are formed as part of the initial insulating layer stack structure before the conductive layers are deposited. This preliminary formation of the layered structure with integrated sacrifice layers allows the stress-management function to be built-in from the start, avoiding the need for additional complex manufacturing steps later in the process. The sacrifice layers are positioned and configured in advance to prevent deflection and buckling during subsequent manufacturing operations.
Solution Approach 2:
The patent employs parameter changes in the form of alternating material compositions and thicknesses for different insulating layers and sacrifice layers. By varying the physical and mechanical parameters (such as material type, layer thickness, and elastic properties) of alternating layers, the structure achieves differential stress distribution that prevents buckling while maintaining ease of manufacture through standard thin-film deposition techniques.
3Ease of manufacture
If insulating layers are allowed to deflect freely, then the manufacturing process is simpler, but conductive layers become disconnected
Solution Approach 1:
The patent applies local quality by allowing controlled deflection in specific regions (first insulating layers) while maintaining flatness in other regions (second insulating layers). The sacrifice layers are strategically positioned to provide local stress relief where needed, preventing the transmission of deflection-induced stresses to the conductive layers. This localized stress management ensures conductive layer continuity and embedding success without requiring complete rigidification of the entire insulating structure.
Data Source
AI summary
A semiconductor memory device includes a first region where a plurality of conductive layers, a plurality of insulating layers, a semiconductor layer, and a gate insulating layer are formed and a second region different from the first region above a substrate. The plurality of conductive layers include a plurality of first conductive layers and a plurality of second conductive layers. The semiconductor memory device includes a plurality of first films different from the first conductive layers disposed in same layers as the plurality of first conductive layers in the second region and a plurality of second films different from the second conductive layers and the first films disposed in same layers as the plurality of second conductive layers in the second region.