3D Memory Floorplan With Face-to-Face Page Buffer Alignment
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Solution Overview
Problem
Planar memory cells face challenges in scaling due to process technology limitations, leading to a density ceiling, while 3D memory cell stacking improves bit density but requires efficient integration of page buffer circuits and bonding structures.
Innovation Solution
A 3D memory architecture with face-to-face bonding of semiconductor structures, incorporating page buffer circuits and bonding dielectric layers, allowing for efficient electrical coupling and reduced routing congestion through optimized placement and alignment of memory planes and page buffer circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes, then memory density is improved, but process technology becomes challenging and costly
Solution Approach 1:
The patent transitions from planar (2D) memory cell scaling to three-dimensional vertically-stacked memory cell architecture. By stacking multiple memory cell layers vertically above the substrate, the invention achieves higher memory density without requiring further reduction of lateral feature sizes, thereby avoiding the manufacturing challenges and costs associated with extreme planar scaling.
2Quantity of substance
If memory cells are stacked vertically, then bit density in the memory array is improved, but integration of page buffer circuits becomes more complex
Solution Approach 1:
The patent places page buffer circuits in a separate semiconductor structure that is bonded face-to-face with the memory array structure. This spatial separation in the vertical dimension allows memory cells to be stacked for high density while page buffer circuits are positioned independently, reducing integration complexity and enabling parallel processing of multiple memory planes.
Solution Approach 2:
The patent divides the memory device into two separate semiconductor structures: one containing the memory array and another containing the page buffer circuits. These structures are then bonded together face-to-face, allowing independent optimization of each component and simplifying the overall integration process while maintaining high bit density.
3Productivity
If page buffer circuits are positioned to overlap memory plane boundaries, then routing efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces bonding dielectric layers with conductive bonding contacts as intermediaries between the memory array structure and the page buffer circuit structure. These bonding layers facilitate precise electrical connections across the face-to-face bonded interface, enabling page buffer circuits to efficiently serve multiple memory planes while maintaining manufacturable alignment tolerances through the intermediary bonding structure.
Data Source
AI summary
A three-dimensional (3D) memory includes a first semiconductor structure having a 3D memory array, wherein the 3D memory array includes a plurality of memory planes, and a second semiconductor structure having a plurality of page buffer circuits, wherein each memory plane has a plurality of bit lines oriented in a bit line direction, a memory-plane-boundary, and a fixed location on the first semiconductor structure, each page buffer circuit has a page-buffer-circuit-boundary, the first semiconductor structure and the second semiconductor structure are bonded to each other in a face-to-face orientation, and a first memory-plane-boundary of a first memory plane, and a first page-buffer-circuit-boundary of a first page buffer circuit, are vertically aligned with each other such that a first portion of the first page-buffer-circuit-boundary is offset from the first memory-plane-boundary in the bit line direction so as to be non-overlapping with an area defined by the first memory-plane-boundary.