3D Memory Staircase Contacts With Buffer Grooves Against Breakdown
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing integration of three-dimensional memory layers leads to deep contact holes, causing gate layer breakdown and potential short circuits, which are exacerbated by thickness adjustments to prevent breakdown, leading to non-uniformity and increased resistance.
Innovation Solution
A fabrication method involving the formation of a laminated structure with exposed interlayer insulation layers, a buffer layer covering these layers, and subsequent removal of buffer layer sidewalls to create spacing grooves, followed by dielectric layer filling and contact hole formation, replacing dummy gate layers with conductive materials to maintain uniformity and prevent short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the gate layer region for forming the contact hole is increased to prevent gate layer breakdown, then the reliability of the contact hole formation is improved, but the uniformity of the material in this region is reduced, causing gaps and increasing resistance in adjacent regions
Solution Approach 1:
The patent introduces a buffer layer as a separate component between the gate layer and the contact hole formation region. This buffer layer is selectively removed to create spacing grooves, segmenting the structure into protected gate regions and contact access regions. This segmentation allows the gate layer to maintain its original uniform thickness while still providing breakdown protection through the buffer layer's sacrificial role.
Solution Approach 2:
The buffer layer acts as an intermediary element that mediates between the gate layer and the contact hole formation process. By removing the buffer layer to create spacing grooves, the patent provides a controlled interface that protects the gate layer from direct contact hole etching damage, preventing breakdown without requiring changes to the gate layer thickness or composition.
2Reliability
If the thickness of the gate layer is increased in the contact hole region, then the gate layer breakdown is prevented, but the thickness of adjacent regions is reduced, leading to increased resistance values
Solution Approach 1:
The buffer layer creates a segmented structure where the gate layer maintains uniform thickness across all regions, while the contact hole access is provided through the removed buffer layer spacing grooves. This segmentation eliminates the need to vary gate layer thickness, thereby preventing both breakdown and adjacent region resistance increases.
Solution Approach 2:
The buffer layer is formed preliminarily over the gate layer before contact hole formation. Its selective removal creates spacing grooves that pre-establish the contact access path, protecting the gate layer from etching damage before the contact hole formation process begins. This preliminary protective structure prevents the need for subsequent thickness adjustments.
3Reliability
If the depth of the contact hole is increased to reach deeper gate layers in high integration structures, then the electrical connection between external circuits and gate layers is improved, but the probability of gate layer breakdown during contact hole formation is increased
Solution Approach 1:
The buffer layer serves as a protective intermediary that shields the gate layer from the harmful effects of deep contact hole etching. By selectively removing the buffer layer to create spacing grooves, the patent provides a controlled interface that allows deep contact holes to be formed while preventing direct etching damage to the gate layer, thus enabling deep connections without increasing breakdown risk.
Solution Approach 2:
The buffer layer provides beforehand cushioning protection to the gate layer against the mechanical and chemical stresses of deep contact hole formation. This sacrificial layer absorbs the etching damage that would otherwise directly affect the gate layer, enabling the formation of deep contact holes necessary for high integration while protecting the gate layer from breakdown.
Data Source
AI summary
A method of fabricating a three-dimensional memory includes forming a laminated structure including stacked dummy gate layers and interlayer insulation layers on one side of a substrate. The respective adjacent dummy gate layers and interlayer insulation layers form staircase stairs. At least a part of the interlayer insulation layer of each of the staircase stairs is exposed. The method also includes forming a buffer layer covering the staircase stairs. The method further includes removing a part of the buffer layer covering the sidewalls of the staircase stairs to form spacing grooves. The method further includes forming a dielectric layer that fills the spacing grooves and covers the staircase stairs. The method further includes forming a contact hole penetrating through the dielectric layer and the buffer layer and extending to the dummy gate layer farthest from the substrate.