3D Memory Channel Structure for P-Well Bulk Erase Reliability
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Solution Overview
Problem
Current 3D NAND memory devices face challenges with sidewall selective epitaxial growth (SEG) due to residue effects on semiconductor channels, leading to variations in thickness and profile, and gate-induced-drain-leakage (GIDL) erase operations suffer from low reliability and slow erase speed.
Innovation Solution
A 3D memory device design featuring an N-type doped semiconductor layer deposited along the sidewalls of channel structures, allowing for P-well bulk erase operations instead of GIDL erase, and separating hole and electron current paths for erase and read operations, respectively, without the need for an inversion channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If sidewall selective epitaxial growth (SEG) is used to form semiconductor channels, then vertical channel structures can be formed, but residue effects cause variations in thickness and profile
Solution Approach 1:
The patent removes the problematic residue layer formed during SEG process by introducing a dedicated removal step. The residue layer that causes thickness and profile variations is extracted/removed to achieve uniform semiconductor channels, while preserving the beneficial vertical structure formation capability of SEG.
Solution Approach 2:
The patent modifies process parameters by introducing oxygen plasma treatment or chemical etching steps with controlled conditions. By changing the processing parameters (oxygen flow rate, power, etch chemistry, temperature), the residue removal is optimized to achieve uniform channel dimensions without compromising the vertical structure integrity.
2Reliability
If GIDL erase operations are used, then erase function can be achieved, but reliability is low and erase speed is slow
Solution Approach 1:
The patent fundamentally changes the erase mechanism by transitioning from GIDL (gate-induced drain leakage) to channel hot carrier injection. This involves modifying the electrical field distribution and carrier generation parameters through structural changes (semiconductor layer positioning, contact configurations) to enable faster and more reliable erase operations through direct carrier injection into the channel.
Solution Approach 2:
The patent replaces the indirect GIDL-based erase mechanism with a direct channel hot carrier injection mechanism. This substitution changes the physical mechanism from field-induced leakage current to direct carrier acceleration and injection, achieving both improved reliability and faster erase speeds.
3Ease of operation
If inversion channel is used for read operations, then read function can be achieved, but source select gate control is complex
Solution Approach 1:
The patent removes the inversion channel structure from the device architecture. By eliminating the need for inversion channel formation, the source select gate control is simplified as direct majority carrier conduction is used instead, reducing the complexity of gate voltage sequencing and control schemes.
Solution Approach 2:
The patent inverts the conventional approach by using direct majority carrier conduction instead of minority carrier inversion. This conceptual inversion simplifies the control mechanism by eliminating the need to create and control inversion layers, allowing more straightforward source select gate operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances reliability and speed of erase operations while simplifying control of the source select gate, mitigating issues related to residue variations and GIDL erase limitations.
Implementation Method 1
sidewall selective epitaxial growth (SEG)
Implementation Method 2
P-type doped region of a substrate, an N-type doped semiconductor layer on the P-type doped region
Data Source
AI summary
Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a doped region of a substrate. The doped region includes dopants of a first type. The 3D memory device also includes a semiconductor layer on the doped region. The semiconductor layer includes dopants of a second type. The first type and the second type are different from each other. The 3D memory device also includes a memory stack having interleaved conductive layers and dielectric layers on the semiconductor layer. The 3D memory device further includes a channel structure extending vertically through the memory stack and the semiconductor layer into the doped region, a semiconductor plug extending vertically into the doped region, the semiconductor plug comprising dopants of the second type, and a source contact structure extending vertically through the memory stack to be in contact with the semiconductor plug.