3D Memory Pad Structure With Bypass Via for Reliable Bonding
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Solution Overview
Problem
The integration of two-dimensional semiconductor memory devices is limited due to the high cost and complexity of fine pattern formation, necessitating the development of three-dimensional structures to enhance performance and reliability while reducing costs.
Innovation Solution
A semiconductor memory device with a peripheral circuit structure and a cell structure featuring multiple contact plugs and metal pads, along with a bypass via to improve electrical connections and reduce arcing, allowing for increased integration and efficiency in hydrogen ion pathways.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional semiconductor memory devices use fine pattern formation to increase integration, then integration is improved, but manufacturing cost and complexity increase significantly
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell structures to three-dimensional vertically stacked memory cell structures. Multiple memory cell layers are stacked along the vertical direction, with each layer containing memory cells formed over active regions. This dimensional change enables significantly higher integration density without requiring progressively finer lateral pattern dimensions, thereby avoiding the exponential cost increase associated with advancing fine pattern formation capabilities.
2Manufacturing precision
If three-dimensional memory cell structures are implemented to increase integration, then integration is improved, but electrical connection reliability and arc prevention become challenging
Solution Approach 1:
The patent implements a multi-layer pad structure with different metal materials at different locations to optimize local electrical properties. The pad structure includes a first pad electrode, second pad electrode, and third pad electrode with varying materials (e.g., tungsten, copper, aluminum) positioned at different heights and locations. This local differentiation ensures optimal electrical connection reliability and arc prevention at each specific interface while maintaining high overall integration density.
Solution Approach 2:
The patent employs composite material structures in the pad electrodes, combining multiple metal materials with different properties. The pad structure integrates tungsten (for mechanical strength and low resistivity), copper (for high electrical conductivity), and aluminum (for ease of fabrication and compatibility) in a multi-layer configuration. This composite approach leverages the advantages of each material to achieve superior electrical connection reliability and arc resistance in the three-dimensional structure.
Data Source
AI summary
A semiconductor memory device includes a peripheral circuit structure including a peripheral circuit and a first bonding pad, the first bonding pad connected to the peripheral circuit, a cell structure on the peripheral circuit structure, the cell structure including a second bonding pad bonded to the first bonding pad, and a pad structure on the cell structure. The cell structure includes a cell substrate having a first face, a second face opposite to the first face, a first contact plug extending through the cell substrate and connected to an electrode layer, and a second contact plug extending through the cell substrate and connected to the cell substrate. Each of the first contact plug and the second contact plug is connected to the pad structure, and a bypass via is in contact with the pad structure on the second face.