3D Memory Device Parasitic Capacitance Balancing
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Solution Overview
Problem
Three-dimensional memory devices face increased leakage current and reliability issues due to parasitic capacitance imbalance between word lines and bit lines in two-dimensional cell arrays, which affects operating speed and reliability.
Innovation Solution
A three-dimensional memory device structure is developed with a base insulating layer, alternately stacked word lines and interlayer insulating layers, bit lines with protruding and penetrating portions, and a dielectric layer between the outer electrode and bit lines to form a parasitic capacitor, reducing capacitance imbalance and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a two-dimensional cell array structure is used to increase integration density, then device complexity is reduced, but leakage current increases and reliability deteriorates due to parasitic capacitance imbalance
Solution Approach 1:
The patent transitions from a two-dimensional cell array structure to a three-dimensional vertical cross-point memory structure. Word lines are stacked vertically with bit lines intersecting them in three-dimensional space, allowing memory cells to be arranged in multiple layers. This dimensional change increases integration density while maintaining balanced parasitic capacitance between word lines and bit lines, thereby reducing leakage current and improving reliability.
Solution Approach 2:
The patent introduces a dielectric layer specifically at the intersection regions where bit lines contact word lines in the vertical stack. This localized modification adjusts the parasitic capacitance distribution at critical points, balancing the electrical characteristics between word lines and bit lines without affecting the overall three-dimensional structure, thus reducing leakage current while maintaining high integration density.
2Productivity
If cell array size is increased to improve memory capacity, then productivity increases, but leakage current increases and reliability deteriorates
Solution Approach 1:
The patent employs a three-dimensional vertical stacking architecture where multiple word lines are stacked vertically and intersected by bit lines in three-dimensional space. This allows memory capacity to be increased by adding more layers and cells vertically rather than expanding the planar area, thereby maintaining balanced parasitic capacitance and reducing leakage current even as memory capacity scales up.
3Reliability
If parasitic capacitance imbalance occurs between word line and bit line, then device complexity remains simple, but operating speed decreases and reliability deteriorates
Solution Approach 1:
The patent introduces a dielectric layer specifically at the bit line contact regions with word lines in the vertical stack. This localized modification increases the parasitic capacitance of bit lines to match that of word lines, balancing the electrical characteristics. This capacitance balancing improves both reliability and operating speed by ensuring uniform signal behavior across the memory array.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure effectively reduces parasitic capacitance imbalance, enhancing the operating speed and reliability of three-dimensional memory devices by optimizing capacitance distribution and using high-k dielectric materials for improved performance.
Implementation Method 1
a dielectric layer between the outer electrode and the first portions of the ones of the bit lines and the dielectric layer surrounds a side surfaces of the first portions of ones of the bit lines in plan view
Implementation Method 2
reducing imbalance of a parasitic capacitance between a word line and a bit line
Data Source
AI summary
A three-dimensional memory device includes a base insulating layer on a substrate, a stack structure including word lines and first interlayer insulating layers which are alternately stacked on the base insulating layer, and a second interlayer insulating layer on an uppermost one of the word lines, bit lines that are in the stack structure and spaced apart from each other in a first direction parallel to a top surface of the substrate, each bit line including a first portion that protrudes from a top surface of the stack structure and a second portion that are in the stack structure, an outer electrode on the stack structure and on the first portions of the bit lines, and a dielectric layer between the outer electrode and the first portion of the bit line and surrounding a side surface of the first portion of the bit line in plan view.