3D Nonvolatile Memory Capacitor Contacts for Reliable Vertical Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current nonvolatile memory devices face challenges in achieving high integration, small size, and low cost while maintaining high operation reliability, particularly in three-dimensional (3D) configurations.
Innovation Solution
The proposed solution involves a nonvolatile memory device with a peripheral circuit structure and a cell array structure that includes a staircase-shaped gate electrode configuration, capacitor core contact structures, and capacitor gate contact structures, which are electrically connected to the peripheral circuit through insulating layers, allowing for efficient communication and enhanced reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D nonvolatile memory devices are used to achieve high integration and small size, then integration density and device size are improved, but operation reliability deteriorates due to increased complexity and potential electrical interference
Solution Approach 1:
The memory device is divided into distinct functional regions: a cell array structure containing memory cells, a peripheral circuit structure containing control circuits, and connection areas with contact structures. This segmentation allows each region to be optimized independently while maintaining overall reliability through reduced electrical interference between functional blocks.
Solution Approach 2:
The patent transitions from planar 2D memory architecture to three-dimensional 3D memory architecture by stacking gate electrodes and insulating layers vertically to form capacitor structures. This vertical stacking enables high integration density while maintaining electrical isolation through insulating layers, thereby improving integration without compromising reliability.
2Productivity
If capacitor core contact structures are positioned to overlap peripheral circuits in vertical direction, then connection efficiency and integration are improved, but electrical interference between capacitor and peripheral circuit increases
Solution Approach 1:
An insulating layer is introduced as an intermediary between the capacitor core contact structure and the peripheral circuit. This insulating layer acts as a mediator that enables vertical stacking for efficient connection while simultaneously providing electrical isolation to prevent harmful interference between the capacitor and peripheral circuit components.
Solution Approach 2:
The insulating layer is selectively positioned in the connection area where capacitor core contact structures overlap with peripheral circuits. This local application of insulation provides targeted electrical isolation precisely where needed, allowing efficient vertical connections while eliminating electrical interference in the specific problematic region without affecting other areas.
3Quantity of substance
If staircase-shaped gate electrode configuration is used in connection area, then integration density and space utilization are improved, but manufacturing complexity increases
Solution Approach 1:
The gate electrodes in the connection area are designed with a staircase shape rather than a uniform rectangular configuration. This dynamic, stepped arrangement allows the gate electrodes to progressively recede in the vertical direction, enabling better space utilization and integration density while still being manufacturable through standard semiconductor fabrication processes.
Data Source
AI summary
A vertically-integrated nonvolatile memory device includes a peripheral circuit structure with a peripheral circuit therein, and cell array structure that is bonded to the peripheral circuit structure, and has a cell area and a connection area therein. The cell area includes a plurality of gate electrodes and a plurality of insulating layers alternately stacked, in the connection area. The plurality of gate electrodes include a cell stack having a staircase shape, a plurality of capacitor core contact structures configured to pass through the cell stack in the cell area, and a plurality of capacitor gate contact structures connected to the plurality of gate electrodes in the connection area. Each of the plurality of capacitor core contact structures includes: (i) a first core conductor electrically connected to the peripheral circuit, and (ii) a first cover insulating layer extending between the first core conductor and the plurality of gate electrodes, and constitutes a capacitor in which the first core conductor, the first cover insulating layer, and the plurality of gate electrodes are connected to the peripheral circuit.