3D Memory Cell Capacitor Structure for Higher Integration
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Solution Overview
Problem
Conventional two-dimensional semiconductor memory devices face limitations in increasing their degree of integration due to physical constraints in ultra-high-density manufacturing processes, necessitating the development of three-dimensional semiconductor memory devices with enhanced memory window characteristics.
Innovation Solution
A three-dimensional semiconductor memory device is designed with memory cells stacked vertically, featuring cell transistors and capacitors with embossed-shaped electrodes and through holes, where the inner surfaces of the electrodes have concave and convex portions, and a capacitor insulating layer extending in the vertical direction to increase cell capacitance and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional two-dimensional semiconductor memory devices are used, then manufacturing processes are simpler, but the degree of integration is limited due to physical constraints
Solution Approach 1:
The patent transitions from conventional two-dimensional planar memory cell structures to three-dimensional vertically stacked memory cells. Multiple memory cells are stacked along the vertical direction, with each cell comprising a transistor and capacitor arranged in three dimensions. This dimensional transition enables significantly higher degree of integration by utilizing the vertical space above the substrate rather than being constrained to planar expansion.
Solution Approach 2:
The patent implements nested structures where capacitors are formed within through-holes of upper electrodes, and multiple memory cells are stacked within a vertical column. The capacitor insulating layer and second electrode are nested within the through-hole of the first electrode, creating a compact nested arrangement that maximizes space utilization and increases integration density.
2Reliability
If conventional planar capacitors are used, then fabrication is easier, but cell capacitance is insufficient for high-performance memory operation
Solution Approach 1:
The patent employs embossed-shaped electrodes with concave and convex portions on their inner surfaces rather than flat planar surfaces. The first electrode and second electrode feature curved and embossed geometries that increase the effective surface area for charge storage. This curvature and embossing enhance the capacitor's cell capacitance and improve memory window characteristics while maintaining compatibility with standard semiconductor fabrication processes.
Solution Approach 2:
The capacitor structure incorporates through-holes penetrating the first electrode, creating a porous or hollow internal structure. The capacitor insulating layer and second electrode fill these through-holes, effectively increasing the capacitance by providing additional charge storage interfaces without significantly increasing the lateral footprint. This porous configuration enhances memory window characteristics while managing fabrication complexity.
Data Source
AI summary
A three-dimensional (3D) semiconductor memory device includes a plurality of memory cells stacked in a vertical direction, each of the plurality of memory cells including a cell transistor and a cell capacitor. The cell capacitor includes a first electrode connected to a first source/drain region of the cell transistor, wherein a through hole is formed in the first electrode and the inner surface of the first electrode is formed in a shape having concave portions and convex portions in plan view, a capacitor insulating layer in the through hole, and a second electrode in the capacitor insulating layer and filling the through hole.