3D Vertical Memory Structure With Integrated Capacitor Layers
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Solution Overview
Problem
Current semiconductor devices face limitations in increasing integration and simplifying the manufacturing process, particularly for non-volatile memory devices, as they are constrained by two-dimensional layouts, necessitating the development of three-dimensional vertical structures.
Innovation Solution
A semiconductor device design featuring a gate stacking structure with interlayer insulating layers and gate electrodes alternately stacked, along with a channel structure passing through the gate stacking structure, and capacitor electrodes with dielectric layers, allowing for increased integration and simplified manufacturing by utilizing existing substrate and wiring layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional layout is used for memory devices, then manufacturing process is simpler, but integration capacity is limited
Solution Approach 1:
The patent transitions from two-dimensional planar memory structures to three-dimensional vertical structures by stacking multiple memory cell layers vertically. The gate stacking structure includes multiple gate electrodes and interlayer insulating layers stacked in the vertical direction, enabling increased integration capacity while maintaining manufacturability through standardized layer-by-layer fabrication processes.
2Quantity of substance
If three-dimensional vertical structures are implemented, then integration capacity increases, but manufacturing process complexity increases
Solution Approach 1:
The gate stacking structure is segmented into multiple discrete layers including gate electrodes and interlayer insulating layers stacked alternately. This segmentation allows each layer to be formed and processed independently using standard semiconductor fabrication techniques, reducing overall manufacturing complexity while achieving high integration capacity.
Solution Approach 2:
The gate stacking structure serves multiple functions simultaneously: it provides electrical connection between substrates, acts as a memory cell structure for data storage, and enables vertical integration for increased capacity. The second capacitor electrode on the same layer as existing components multiplies the utility of each fabricated layer.
3Adaptability or versatility
If additional layers and structures are added for capacitor electrodes, then device functionality is enhanced, but manufacturing complexity increases
Solution Approach 1:
The second capacitor electrode is merged with existing structural layers, specifically positioned on the same layer as at least one of the wiring layer, second substrate, first horizontal conductive layer, or gate electrode. This merging eliminates the need for separate capacitor electrode fabrication steps, enhancing device functionality while avoiding additional manufacturing complexity.
Data Source
AI summary
A semiconductor device includes a first substrate; a wiring layer on the first substrate; a second substrate on the wiring layer and including a conductive material; a first horizontal conductive layer and a second horizontal conductive layer sequentially stacked on the second substrate and connected to the second substrate; a gate stacking structure including an interlayer insulating layer and a gate electrode alternately stacked on the second horizontal conductive layer; a channel structure passing through the gate stacking structure and connected to the second substrate; a first capacitor electrode on a same layer as the second substrate; a second capacitor electrode overlapping the first capacitor electrode; and a first dielectric layer between the first capacitor electrode and the second capacitor electrode, wherein the second capacitor electrode is on a same layer as at least one of the wiring layer, the second substrate, the first horizontal conductive layer, or the gate electrode.