3D Memory Capacitor Electrode Layout for Higher Integration
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity and integration while maintaining reliability.
Innovation Solution
A semiconductor device design featuring a first structure with a peripheral circuit and a second structure, including a stack structure with alternating gate electrodes and insulating layers, and parallel capacitor electrodes, along with memory vertical structures and separation structures, to enhance integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally to increase data storage capacity, then storage capacity increases, but device complexity increases
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional stacking, where multiple memory cell layers are vertically stacked above each other. This dimensional change allows significantly increased storage capacity within the same footprint area, addressing the contradiction by utilizing vertical space to accommodate more storage elements without proportionally increasing overall device complexity.
Solution Approach 2:
The patent implements a nested structure where capacitor electrodes are embedded within the stack structure, with first and second capacitor electrodes positioned at different vertical levels and separated by insulating layers. This nesting approach allows multiple functional elements (memory cells, capacitors, insulating layers) to be integrated in a compact hierarchical arrangement, increasing storage capacity while managing device complexity through efficient spatial organization.
2Productivity
If capacitor electrodes are added to enhance integration, then integration increases, but manufacturing complexity increases
Solution Approach 1:
The patent combines the formation of capacitor electrodes with the existing stack structure fabrication process. The first and second capacitor electrodes are integrated into the stack structure during the same manufacturing sequence, sharing common process steps such as material deposition, patterning, and etching. This merging of fabrication steps increases integration while avoiding the need for separate, complex manufacturing processes.
Solution Approach 2:
The stack structure serves multiple functions simultaneously: it acts as both the memory cell structure and the capacitor structure. The same alternating layers of conductive and insulating materials that form the memory cells also form the capacitor electrodes and dielectric layers, eliminating the need for separate dedicated capacitor fabrication processes and thereby increasing integration without proportionally increasing manufacturing complexity.
3Reliability
If alternating insulating layers with different materials are used, then reliability increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs different insulating materials at different positions within the stack structure: a first insulating material for the lower insulating layer and a second insulating material for the upper insulating layer. Each material is selected to optimize performance for its specific location - the lower layer material provides appropriate electrical isolation for the first capacitor electrode, while the upper layer material provides isolation for the second capacitor electrode. This localized optimization improves reliability without requiring excessive manufacturing precision across the entire structure.
Solution Approach 2:
The patent uses composite material construction with alternating layers of different insulating materials (first insulating material and second insulating material) in the stack structure. This composite approach allows each material to contribute its specific properties to the overall structure, improving reliability through material diversity while the standardized layering process keeps manufacturing precision requirements manageable.
Data Source
AI summary
A semiconductor device includes a first structure including a peripheral circuit and a second structure on the first structure. The second structure includes: a stack structure including first and second stack structures; separation structures passing through the first stack structure; a memory vertical structure between the separation structures and passing through the first stack structure; and a capacitor including first and second capacitor electrodes passing through the second stack structure and extending parallel to each other. The first stack structure includes spaced apart gate electrodes and interlayer insulating layers alternately stacked therewith. The second stack structure includes spaced apart first insulating layers, and second insulating layers alternately stacked therewith. Each of the first and second capacitor electrodes has a linear shape. The first and second insulating layers include a different material from each other. The second insulating layers include the same material as the interlayer insulating layers.