3D Memory Capacitor Structure With Penetration Vias for High Capacitance
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity and enhancing performance, particularly in implementing three-dimensional memory cell structures.
Innovation Solution
A semiconductor device design featuring a gate stacking structure with interlayer insulation, penetration structures, and capacitor wiring configurations that enhance capacitance in a small area by electrically connecting and insulating multiple penetration structures with capacitor wirings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If penetration structures are increased to enhance capacitance, then the capacitance increases, but the area occupied increases
Solution Approach 1:
The patent transitions from a planar capacitor arrangement to a three-dimensional structure by having penetration structures extend vertically through multiple interlayer insulation layers. Multiple gate electrodes are stacked in the vertical dimension, with penetration structures connecting to capacitor wirings at different heights, thereby increasing capacitance without proportionally increasing the planar area occupied.
Solution Approach 2:
The penetration structures are nested within the gate stacking structure, with multiple penetration structures arranged in a compact configuration where they share common regions of the interlayer insulation layers. The capacitor wirings are positioned to overlap with the penetration structures in the planar view, creating a nested arrangement that maximizes capacitance within a confined area.
2Quantity of substance
If multiple capacitor wirings are added to increase capacitance, then the capacitance increases, but the device complexity increases
Solution Approach 1:
The gate electrodes serve multiple functions: they act as control gates for the transistor and simultaneously as one electrode of the capacitor structure. The penetration structures serve dual purposes by providing electrical connection between different wiring layers and forming part of the capacitor electrode system. This multi-functionality reduces the need for separate dedicated capacitor components.
Solution Approach 2:
The patent merges the gate electrode structure with the capacitor electrode structure. The first and second capacitor wirings are positioned to overlap with the penetration structures, creating a combined structure where the gate stacking region also functions as the capacitor region. This merging eliminates the need for separate capacitor electrode structures and reduces overall device complexity.
Data Source
AI summary
According to an aspect of the present disclosure, a semiconductor device includes a cell structure including a gate stacking structure in a first region and an insulation structure in a second region, a first wiring portion disposed on a first surface of the cell structure, a second wiring portion disposed on a second surface of the cell structure opposite to the first surface, a channel structure at least partially penetrating the gate stacking structure and being electrically coupled with the first wiring portion and the second wiring portion, and a capacitor structure including a plurality of penetration structures. The gate stacking structure includes a plurality of gate electrodes while interposing an interlayer insulation layer therebetween. Each of the plurality of penetration structures at least partially penetrates at least a portion of the insulation structure.