3D Memory Cell Capacitor Structure for Scaling-Limited Capacitance
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Solution Overview
Problem
Scaling memory cells in three-dimensional memory arrays is limited by the reduction in capacitance, which affects the ability to properly store and maintain logic states, leading to insufficient capacitance for proper memory cell operation.
Innovation Solution
Incorporating a capacitor structure where a second portion extends into a dielectric layer between levels of the memory array, compensating for the reduction in capacitance of the first portion, allowing for reduced memory cell pitch and increased density while maintaining proper logic state storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell dimensions are reduced to increase density, then memory cell pitch is reduced and density increases, but capacitance decreases leading to insufficient capacitance for proper memory cell operation
Solution Approach 1:
The capacitor structure transitions from a planar two-dimensional configuration to a three-dimensional structure by extending the capacitor into the dielectric layer between memory array levels. This vertical extension adds a new dimension to the capacitor geometry, increasing its volume and capacitance without occupying additional lateral space, thereby maintaining high memory cell density while achieving sufficient capacitance for reliable operation
Solution Approach 2:
The capacitor is nested within the existing memory array structure by extending into the dielectric layer that already exists between levels. The capacitor structure is positioned within the vertical space between memory cell levels, utilizing the available three-dimensional space without interfering with the horizontal layout of memory cells, thus achieving increased capacitance while maintaining high density
2Length of moving object
If capacitor dimensions are reduced to match scaled memory cell size, then memory cell size is reduced, but capacitance becomes insufficient for storing logic states
Solution Approach 1:
The capacitor extends vertically into the dielectric layer between memory array levels, adding a third dimension to the capacitor structure. This vertical extension compensates for the reduction in horizontal dimensions, maintaining sufficient capacitance volume while allowing the memory cell footprint to be scaled down for higher density
Solution Approach 2:
The capacitor geometry is changed from a planar configuration to a three-dimensional structure with extended height. By changing the spatial parameters of the capacitor (extending into the vertical dimension), the capacitance is maintained or increased even as the lateral dimensions are reduced to achieve smaller memory cell size
3Quantity of substance
If traditional scaling methods are used to reduce memory cell pitch, then density increases, but capacitance reduction limits further scaling
Solution Approach 1:
Instead of continuing to scale horizontally, the capacitor structure utilizes the vertical dimension by extending into the dielectric layer between memory array levels. This approach to scaling adds capacitance volume in the vertical direction, enabling further memory cell density improvement without being constrained by traditional horizontal scaling limitations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables increased memory cell density and storage capacity by ensuring sufficient capacitance for memory cell function, even with reduced dimensions, thereby overcoming the limitations of traditional scaling methods.
Implementation Method 1
a capacitor coupled with the channel portion and operable to store a logic state of the memory cell
Data Source
AI summary
Methods, systems, and devices for memory cell capacitor structures for three-dimensional memory arrays are described. A memory device may include a memory array including multiple levels of memory cells that are each separated from another level by a respective dielectric layer. A memory cell at a first level of the memory array may include a channel portion and a capacitor operable to store a logic state of the memory cell. A first portion of the capacitor may be located between the channel portion and a voltage source coupled with the memory cell. A second portion of the capacitor may be in a cavity in a dielectric layer between the first level and a second level of the memory array. The second portion of the capacitor may be located between the channel portion and a word line coupled with a channel portion of a second memory cell at the second level.