3D Capacitor Stack Memory Architecture Beyond Planar Scaling
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Solution Overview
Problem
Planar memory cells face density limitations and fabrication challenges as feature sizes approach a lower limit, making it costly to further shrink memory density.
Innovation Solution
A 3D memory architecture is introduced with a stack structure comprising alternately stacked conductive layers, conductive vias, and isolation structures, along with a capacitor stack structure featuring electrode plates and select electrodes, allowing for increased memory density and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density is improved, but manufacturing cost increases and fabrication becomes challenging
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to a three-dimensional (3D) memory architecture. The memory array is formed with vertical stacking of conductive layers, insulating layers, and active regions, enabling memory density improvement without further shrinking lateral feature sizes. This dimensional change resolves the fabrication challenges and cost increases associated with continued planar scaling.
2Quantity of substance
If feature sizes of memory cells are reduced, then memory density is improved, but process complexity and cost increase
Solution Approach 1:
The patent employs vertical stacking of multiple conductive layers and insulating layers to achieve higher memory density without reducing lateral feature sizes. The 3D memory architecture uses alternating conductive and insulating layers forming a stacked structure, which simplifies the manufacturing process compared to continued planar scaling while achieving the same density improvement goal.
3Quantity of substance
If planar process techniques are used for further scaling, then memory density is improved, but manufacturing cost increases
Solution Approach 1:
The patent adopts a three-dimensional memory architecture with vertically stacked conductive layers and insulating layers, replacing the planar process approach. This dimensional transition enables memory density improvement through vertical stacking rather than lateral shrinking, thereby avoiding the increased manufacturing costs associated with advanced planar scaling processes.
Data Source
AI summary
Memory devices and fabricating methods thereof are disclosed. In some implementations, the disclose memory device comprises a capacitor stack structure and an array of transistors. The capacitor stack structure comprises first electrode plates and second electrode plates alternatively stacked along a vertical direction, a common electrode vertically extending through the capacitor stack structure and in contact with the first electrode plates, and select electrodes each extending through the capacitor stack structure and in contact with a corresponding one of the second electrode plates. Each transistor of the array of transistors is coupled with a corresponding one of the select electrodes.