3D Memory Cell Bonding Pad Layout for Dense Low-Capacitance Arrays
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in increasing memory cell density and reducing parasitic capacitance, which are essential for advancing memory device performance and miniaturization.
Innovation Solution
A semiconductor device with a memory cell array featuring vertical and horizontal conductive lines, a data storage element, and a peripheral circuit portion, where bonding pads facilitate metal-to-metal or hybrid bonding between the memory cell array and the peripheral circuit, allowing for multi-level interconnections and improved structural alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory devices are stacked to increase capacity, then memory cell density increases, but parasitic capacitance increases
Solution Approach 1:
The patent transitions from planar two-dimensional memory structures to three-dimensional stacked structures with vertical conductive lines extending through multiple levels. Memory cells are arranged in vertical columns with bit lines, word lines, and storage nodes stacked in the third dimension, enabling increased storage capacity while maintaining reduced parasitic capacitance through optimized vertical interconnections
Solution Approach 2:
The memory device is divided into multiple discrete levels or stacks, with each level containing complete memory cell structures. The vertical conductive lines are segmented into portions at different levels, and isolation structures are placed between levels to electrically separate parasitic capacitance sources, allowing each segment to contribute to total capacity without proportionally increasing overall parasitic effects
2Volume of moving object
If memory devices are miniaturized to increase density, then device size decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary formation of alignment structures and reference features during earlier fabrication steps. Conductive line positions and storage node locations are pre-established with high precision using standardized patterning processes, and subsequent stacking operations align to these pre-formed features, reducing the cumulative precision requirements of multi-step miniaturization processes
Solution Approach 2:
The invention implements nested multi-level structures where smaller memory cell components are vertically integrated within compact footprints. Multiple bit lines, word lines, and storage nodes are nested in vertical columns, with each level containing complete functional units. This nesting approach achieves high density by utilizing vertical space efficiently while maintaining manufacturable dimensions through repeated patterning of standardized cell templates
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances memory cell density and reduces parasitic capacitance, leading to improved performance and miniaturization capabilities in three-dimensional memory devices.
Implementation Method 1
The bonding of the first bonding pad and the second bonding pad includes metal-to-metal bonding or hybrid bonding
Data Source
AI summary
A semiconductor device includes: a memory cell array including a vertical conductive line, a horizontal conductive line, and a data storage element; a peripheral circuit portion disposed at a lower-level than the memory cell array; a first bonding pad structure suitable for electrically connecting the vertical conductive line of the memory cell array and the peripheral circuit portion; and an upper pad disposed at a higher level than the memory cell array and coupled to the data storage element.