3D One-Transistor Memory Cell With Surrounding Channel Structure
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Solution Overview
Problem
The challenge of increasing memory density and capacity in integrated circuits (ICs) while optimizing fabrication and performance of memory components has become increasingly significant with the drive for smaller features.
Innovation Solution
The implementation of a three-dimensional (3D) memory array with one-transistor memory cells featuring a channel region surrounding source and drain regions, utilizing a stack of conductive and insulator materials, and incorporating hysteretic materials to enhance memory cell functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional planar memory cell structures are used, then fabrication is simpler, but memory density and capacity are limited
Solution Approach 1:
The patent transitions from traditional planar memory cell structures to a three-dimensional stacked architecture where multiple memory cells are vertically stacked across multiple substrates. This dimensional change enables significantly higher memory density and capacity while maintaining manageable fabrication complexity through standardized stacking processes.
2Quantity of substance
If transistor size is reduced to increase device density, then more devices fit on the chip, but fabrication optimization becomes increasingly difficult
Solution Approach 1:
By stacking memory cells vertically across multiple substrates, the patent achieves high device density without continuously shrinking transistor dimensions. This three-dimensional arrangement allows standard fabrication processes to be reused across layers, simplifying manufacturing optimization compared to aggressive lateral scaling.
3Reliability
If channel region surrounds source and drain regions, then memory cell performance is enhanced, but device complexity increases
Solution Approach 1:
The patent implements a nested structure where the channel region is positioned to surround both the source and drain regions within the same transistor cell. This nested configuration enhances memory cell performance by improving charge carrier pathways while containing the added structural complexity within a compact arrangement that scales well in three dimensions.
Data Source
Figure 1
Figure 2A~2B
Figure 3A~3B
AI summary
A three-dimensional (3D) memory array may include one-transistor memory cells with a channel around source and drain regions. In one example, a memory cell includes a transistor with a source (222-1) region, a drain region (222-2), an insulator material (224) between the source region and the drain region in a plane substantially parallel to a substrate, a semiconductor material (e.g., a channel region, 210) surrounding the source region and the drain region in the plane, and a hysteretic material (208) surrounding the semiconductor material in the plane. A first conductive line may be coupled with the source region, a second conductive line may be coupled with the drain region, and a third conductive line (220) including a portion of conductive material may surround the hysteretic material in the plane.