3D Memory Cell Storage Structure for Higher Integration Density
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Solution Overview
Problem
Current semiconductor devices face limitations in increasing data storage capacity, particularly in achieving high integration density and efficient data storage structures.
Innovation Solution
The semiconductor devices incorporate three-dimensionally arranged cell transistors and data storage structures, with specific configurations including stacked and spaced transistors, bit lines, word lines, active layers, and data storage structures, utilizing materials like doped polysilicon and dielectric layers to enhance integration density and data storage capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensionally arranged memory cells are used instead of two-dimensionally arranged memory cells, then data storage capacity is increased, but device complexity increases
Solution Approach 1:
The patent implements three-dimensionally arranged memory cells with cell transistors stacked in the vertical direction (first direction perpendicular to the base surface) rather than two-dimensional arrangement. This vertical stacking enables increased data storage capacity by utilizing the third dimension, allowing multiple memory cells to occupy a smaller footprint area on the substrate while maintaining independent electrical control through bit lines and word lines
Solution Approach 2:
The memory device is segmented into multiple independently controllable units, with each memory cell comprising a cell transistor and an data storage structure. This segmentation allows for modular organization where bit lines extend in the first direction to connect to first source/drain regions, and data storage structures connect to second source/drain regions, enabling independent addressing and control of each stacked memory cell
2Productivity
If cell transistors are stacked and spaced apart in the first direction, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent achieves high integration density by transitioning from planar two-dimensional arrangement to three-dimensional vertical stacking of cell transistors in the first direction. Multiple cell transistors are stacked with spacing between them, allowing dense packing in the vertical dimension while maintaining electrical isolation and independent controllability through the gate electrodes and source/drain regions
Solution Approach 2:
Each cell transistor in the stacked configuration maintains its own gate electrode with line shape extending in the second direction, source/drain regions for electrical connection, and associated data storage structures. This local quality ensures that each stacked transistor unit can be independently controlled and manufactured with consistent performance characteristics, facilitating precise manufacturing through standardized modular units
Data Source
AI summary
A semiconductor device includes: cell transistors stacked in a first direction perpendicular to an upper surface of a base, wherein each cell transistor includes a first source/drain region, a second source/drain region, and a gate electrode, a bit line extending in the first direction and electrically connected to the first source/drain regions; and data storage structures electrically connected to the second source/drain regions, wherein each gate electrode has a line shape extending in a second direction parallel to the upper surface, each data storage structure includes a first electrode, a second electrode, and a dielectric layer between the first and second electrodes, wherein the first electrodes are electrically connected to the second source/drain regions, wherein the second electrodes are stacked and spaced apart from each other in the first direction, and wherein each second electrode includes a line portion having a line shape extending in the second direction.