3D Three-Transistor Memory Cell Structure for High Integration
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in miniaturization and high integration due to constraints from static capacitance of capacitors and coupling capacitance between bit lines, limiting reliability and performance.
Innovation Solution
A three-dimensional memory cell structure is implemented with three-transistor memory cells, arranged in a horizontal and vertical configuration, eliminating the need for capacitors and utilizing transistors to facilitate miniaturization and high integration, with bit lines and word lines arranged to optimize connectivity and reduce capacitive constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If capacitor-based memory cells (1T1C) are used, then data storage function is achieved, but static capacitance constraints limit miniaturization and high integration
Solution Approach 1:
The patent extracts and removes the capacitor component from the memory cell structure, transitioning from 1T1C (one transistor, one capacitor) to 3T (three transistors) configuration. This eliminates the static capacitance constraints that limited miniaturization while maintaining data storage functionality through transistor-based charge retention.
Solution Approach 2:
The patent changes the fundamental operating parameters of the memory cell by replacing capacitor-based charge storage with transistor-based charge retention. This parameter change allows the memory cell to function without being constrained by capacitor static capacitance, enabling further miniaturization and high integration.
2Reliability
If capacitor static capacitance is increased to maintain reliability, then data retention improves, but device area increases preventing high integration
Solution Approach 1:
By removing the capacitor from the memory cell structure, the patent eliminates the direct relationship between data retention and capacitor size. The three-transistor configuration achieves data retention through alternative mechanisms that do not require large static capacitance, thereby reducing the memory cell area and enabling high integration.
3Measurement precision
If bit line coupling capacitance is reduced to improve signal integrity, then reading accuracy improves, but device layout complexity increases
Solution Approach 1:
The patent converts the potential harm of coupling capacitance between bit lines into a benefit by using the coupling effect constructively in the three-transistor memory cell operation. The unique transistor configuration allows the memory cell to utilize coupling capacitance for improved reading accuracy while maintaining a regular, scalable layout that does not increase device complexity.
4Productivity
If memory cells are miniaturized to increase integration density, then high integration is achieved, but static capacitance constraints are violated in 1T1C structures
Solution Approach 1:
The patent fundamentally changes the operating parameters by transitioning from capacitor-based to transistor-based charge retention. This parameter change removes the minimum static capacitance requirement that constrained miniaturization, allowing memory cells to be scaled down while maintaining reliability and achieving high integration density.
Solution Approach 2:
The patent moves the charge retention mechanism from a two-dimensional capacitor structure to a three-dimensional transistor configuration, utilizing vertical channel structures and stacked transistor arrangements. This dimensional change enables miniaturization in the planar area while maintaining sufficient charge retention capacity through the three-transistor architecture.
Data Source
AI summary
A semiconductor memory device includes a memory cell array of a three-dimensional structure including a plurality of memory cells repeatedly arranged in a first horizontal direction and a second horizontal direction that are parallel with a main surface of a substrate and cross each other on the substrate and in a vertical direction perpendicular to the main surface, wherein each of the plurality of memory cells includes three transistors. A method of manufacturing a semiconductor memory device includes forming simultaneously a plurality of memory cells arranged in a row in a vertical direction on a substrate, wherein each of the plurality of memory cells includes three transistors.