3D Nanosheet Memory Cell Layout for Higher Density and Lower Leakage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory technologies face challenges in increasing storage density and reducing the occupied area of each device while improving electrical performance.
Innovation Solution
The proposed memory and storage system incorporates a substrate with a control circuit layer and multiple storage structure layers stacked in a specific direction. Each memory cell includes a storage structure and series-connected selection transistors with nanosheet channel structures, sharing a gate structure to enhance control and reduce leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional planar memory cell structures are used, then manufacturing process is simpler, but storage density and integration level are limited
Solution Approach 1:
The patent transitions from planar 2D memory cell layout to a 3D stacked architecture where storage structures are vertically stacked above control circuits. Multiple storage structure layers are stacked in the vertical direction, allowing more memory cells to be integrated within the same footprint area, thereby significantly improving storage density without proportionally increasing device complexity
Solution Approach 2:
The patent implements a nested structure where storage structures are positioned above and integrated with control circuit layers. The memory cell architecture nests the storage structure within the vertical column above the control transistor, creating a compact integrated structure that maximizes space utilization and improves storage density
2Reliability
If conventional channel structures are used, then manufacturing is easier, but leakage current is higher and electrical performance is poorer
Solution Approach 1:
The patent changes the physical parameters of the channel structure by introducing nanosheets with specific thickness and width dimensions. The nanosheet channel structure has controlled thickness (e.g., 3-5 nm) and width, providing better electrostatic control and lower leakage current compared to conventional bulk channels, while maintaining compatibility with existing semiconductor manufacturing processes
Solution Approach 2:
The patent employs composite material structures combining nanosheet channels with high-k dielectric gate materials. This composite approach enables superior electrical performance with reduced leakage current while the manufacturing process remains feasible through adapted standard fabrication techniques
3Area of stationary object
If each selection transistor has independent gate structures, then control flexibility is higher, but occupied area increases and integration level decreases
Solution Approach 1:
The patent merges multiple gate structures into a shared gate that simultaneously controls multiple selection transistors stacked in the vertical direction. This shared gate structure reduces the horizontal footprint area while maintaining vertical stacking architecture, achieving better area efficiency without completely sacrificing control capability through selective gating mechanisms
Data Source
AI summary
Provided are a memory and a storage system. The memory includes: a substrate; a control circuit layer located in the substrate, the control circuit layer including a part of control circuits of the memory; and at least two storage structure layers sequentially stacked on the control circuit layer in a first direction. The first direction is perpendicular to the surface of the substrate. The storage structure layer is connected to the control circuit layer. The storage structure layer includes memory cells arranged in an array. The memory cell includes a storage structure and at least two series-connected selection transistors connected to the storage structure. The at least two series-connected selection transistors are stacked in the first direction. A channel structure of the selection transistor includes at least one layer of nanosheets. The at least two series-connected selection transistors share one gate structure.