3D Memory Cell Stacking to Shorten IC Interconnects
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Solution Overview
Problem
Wires in integrated circuits (ICs) dominate performance, functionality, and power consumption as they degrade with scaling, necessitating new approaches to reduce wire lengths and improve silicon area utilization.
Innovation Solution
3D stacking of semiconductor devices with layer transfer technologies that support the fabrication of active devices on transferred layers, including memory control circuits and arrays, and the use of monolithic 3D integration to reduce wire lengths and enhance silicon area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If 2D planar integration is used, then manufacturing process is simple, but wire lengths are long and silicon area utilization is low
Solution Approach 1:
The patent transitions from 2D planar integration to 3D stacked integration, stacking multiple transistor layers vertically to reduce wire lengths and increase silicon area utilization. This dimensional change allows transistors to be placed closer together in the vertical direction, directly addressing the wire length issue while managing the increased complexity through systematic layer stacking.
2Quantity of substance
If transistor size is scaled down, then transistor density improves, but wire performance degrades
Solution Approach 1:
By stacking transistors in the vertical dimension, the patent achieves higher transistor density without further lateral scaling. This reduces the distance wires need to travel across the silicon area, thereby maintaining wire performance while increasing transistor density. The vertical stacking decouples the trade-off between density and wire length.
3Length of moving object
If 3D stacking is implemented, then wire lengths are reduced, but manufacturing complexity increases
Solution Approach 1:
The patent divides the integrated circuit into multiple discrete transistor layers stacked vertically, with each layer potentially fabricated separately and then bonded together. This segmentation allows for modular manufacturing, where each layer can be optimized independently, and defect isolation is improved. The complexity is managed by breaking down the 3D structure into manageable 2D layers that can be processed using existing fabrication techniques.
Data Source
AI summary
A semiconductor device, the device including: a first level including memory control circuits, the memory control circuits including first transistors, a second level disposed on top of the first level, the second level including a first array of memory cells including second transistors; a third level disposed on top of the second level, the third level including a second array of memory cells including third transistors; a fourth level disposed on top of the third level, the fourth level including a third array of memory cells including fourth transistors, where the second level is bonded to the first level, where the memory control circuits include cache memory, and where the second array of memory cells include a plurality of independently controlled memory units, and a plurality of refresh circuits for the memory units.