3D Vertical Memory Cell Stacking for Density
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Solution Overview
Problem
Conventional volatile memory devices face challenges in increasing storage density without aggressively reducing feature size, due to physical limitations and fabrication constraints in their planar structure.
Innovation Solution
The implementation of a three-dimensional (3-D) structure for volatile memory cells, where memory cells are vertically stacked over each other, allowing for higher storage density without shrinking feature size, using a configuration that includes access lines, data lines, address registers, and sensing circuitry to manage memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional planar structure is used to increase storage density, then feature size must be aggressively reduced, but physical limitations and fabrication constraints prevent further size reduction
Solution Approach 1:
The patent transitions from a two-dimensional planar structure to a three-dimensional vertical structure by stacking multiple memory cell layers above a substrate. This dimensional change allows storage density to increase vertically rather than requiring further horizontal feature size reduction, thereby overcoming the manufacturing precision limitations of conventional planar approaches.
2Quantity of substance
If feature size is reduced to increase storage density, then more memory cells can be packed, but fabrication constraints and physical limitations are reached
Solution Approach 1:
By stacking memory cells vertically in multiple layers, the patent increases the number of memory cells without requiring further reduction of individual feature sizes. This approach maintains fabrication feasibility by operating at existing manufacturing capabilities while achieving higher cell counts through the third dimension.
Solution Approach 2:
The patent implements a nested structure where multiple memory cell layers are stacked vertically, with each layer containing transistors and capacitors that are integrated within the vertical column. This nesting approach allows multiple functional elements to occupy the same footprint area, increasing cell count without compromising fabrication ease.
3Quantity of substance
If planar structure is used, then fabrication is simpler, but storage density cannot be increased without shrinking feature size
Solution Approach 1:
The patent adopts a three-dimensional vertical stacking structure where memory cells are arranged in multiple layers above the substrate. This structural complexity enables significantly higher storage density by utilizing the vertical dimension, trade-offting increased device complexity for substantial gains in storage capacity.
Data Source
AI summary
Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes volatile memory cells located along a pillar that has a length extending in a direction perpendicular to a substrate of a memory device. Each of the volatile memory cells includes a capacitor and at least one transistor. The capacitor includes a capacitor plate. The capacitor plate is either formed from a portion a semiconductor material of the pillar or formed from a conductive material separated from the pillar by a dielectric.