3D Memory Cell Structure for High-Density Low-Power Semiconductors
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving miniaturization, high integration, high operating speed, favorable electrical characteristics, low power consumption, and high reliability while maintaining a small variation in transistor electrical characteristics.
Innovation Solution
A semiconductor device is designed with a specific structure that includes multiple transistors and a capacitor, utilizing metal oxides and conductors to achieve high integration and low power consumption. The device includes a first conductor, a second conductor, insulators, and transistors with metal oxides, which are electrically connected to form a memory cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are stacked to increase storage capacity, then memory capacity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar 2D transistor arrangement to 3D vertical stacking, enabling multiple memory cells to be stacked in the thickness direction. This dimensional change allows increased storage capacity without proportionally increasing footprint area, while the standardized stack structure helps control manufacturing complexity through modular fabrication processes
Solution Approach 2:
The patent implements nested structures where conductors are embedded within insulators, and multiple functional layers are nested vertically. The first conductor is nested in the first insulator, the second conductor in the second insulator, with transistors and capacitors stacked within each other, creating a compact nested architecture that increases density while maintaining manufacturability through systematic layering
2Area of moving object
If transistor size is reduced for miniaturization, then area is reduced, but electrical characteristic variation increases
Solution Approach 1:
The patent applies different material properties and structural characteristics to different regions of the device. The first and second conductors have different configurations, the insulators have different compositions (including high-k materials), and the transistor structures are optimized locally. This local quality differentiation allows miniaturization while maintaining consistent electrical characteristics through region-specific optimization
Solution Approach 2:
The patent employs composite material structures, particularly using high-k insulator materials combined with conventional insulators, and multi-layer conductor configurations. These composite structures provide better electrical performance and reduced variation in miniaturized transistors by combining materials with complementary properties that compensate for scaling effects
3Use of energy by moving object
If refresh operations are reduced for low power consumption, then energy usage is reduced, but data retention reliability may worsen
Solution Approach 1:
The patent implements self-refresh mechanisms where the memory structure maintains its own charge through the capacitor-transistor configuration. The capacitor stores charge locally at each memory cell, and the transistor structure is designed to maintain this charge with minimal leakage, enabling the device to refresh itself with very low external power input, thus reducing overall power consumption while maintaining data retention
Solution Approach 2:
The patent incorporates capacitors in advance within each memory cell structure to cushion against charge loss. These capacitors are pre-configured to store charge and compensate for leakage before it becomes problematic, allowing the memory to maintain data integrity over longer periods with reduced refresh frequency, thereby lowering power consumption while preserving reliability
Data Source
AI summary
A semiconductor device that includes a first conductor (233a1), a second conductor (231), a first transistor (201) over a first insulator, and a second insulator (282) over the first insulator is provided. The first transistor includes a third conductor (242a) and a fourth conductor (242b) that are each electrically connected to a first metal oxide (230), a third insulator (253, 254) over the first metal oxide, and a fifth conductor (260) over the third insulator. The fourth conductor includes a second layer over a first layer. The top surface of the fifth conductor includes a region in contact with the second insulator. The first conductor includes a portion positioned inside an opening of the first insulator, a region in contact with a side surface of the third conductor, and a portion positioned inside an opening of the second insulator. The second conductor includes a region in contact with the second layer and a portion positioned inside an opening of the second insulator. The top surface of the first conductor and the top surface of the second conductor are level with each other.