3D Memory Cells Using Floating-Body Architecture
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Solution Overview
Problem
Current technologies have not successfully realized a cost-effective three-dimensional (3D) array structure for dynamic random-access memory (DRAM) due to its one-transistor-one-capacitor (1T1C) cell structure, limiting the development of high-density DRAM solutions.
Innovation Solution
A novel 3D array structure using floating-body cells is developed, similar to 3D NAND flash memory, which includes a semiconductor material with a floating body surrounded by a dielectric layer, connected to bit and source lines, and gates, enabling ultra-high-density DRAM implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a 3D array structure is used to increase memory capacity, then memory density is improved, but the one-transistor-one-capacitor (1T1C) cell structure makes cost-effective implementation difficult
Solution Approach 1:
The patent transitions from planar 2D memory arrays to three-dimensional stacked architectures, where memory cells are arranged in vertical columns with multiple layers. This dimensional change enables significantly higher memory density by utilizing the third dimension (vertical stacking) rather than only horizontal expansion, directly addressing the need to increase memory capacity while maintaining cost-effectiveness through scalable fabrication processes.
2Ease of operation
If conventional 1T1C DRAM structure is used, then random-access memory functionality is achieved, but 3D array structure implementation is not cost-effective
Solution Approach 1:
The patent employs a multi-functional select transistor architecture where a single select transistor serves multiple memory cells within a column, rather than requiring separate access transistors for each cell. This multi-functionality reduces the overall transistor count and simplifies the 3D structure, making cost-effective implementation feasible while preserving random-access memory functionality through selective word line and bit line activation.
Solution Approach 2:
The patent combines multiple memory cell access functions into a shared select transistor structure. By merging the access control for multiple cells into a single transistor component, the design reduces manufacturing complexity and cost while maintaining the ability to selectively access individual cells through decoded word lines and bit lines in the 3D stacked architecture.
Data Source
AI summary
Various 3D memory cells, array architectures, and processes are disclosed. In an embodiment, a memory cell structure is provided that is formed by a process of alternately depositing multiple semiconductor layers and insulating layers to form a stack, forming vertical bit line holes through the stack using a deep trench process, and forming floating bodies in the semiconductor layers using an isotropic doping process through the bit line holes.