3D Memory Block Layout Around Central Pads to Cut Parasitics
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Solution Overview
Problem
Conventional integrated circuits require additional layout area for transmission wires between pads and memory blocks, leading to increased parasitic resistance and capacitance, which affects signal and power transmission quality.
Innovation Solution
The integrated circuit design symmetrically disposes memory blocks around a pad disposing area, reducing the length of transmission wires and eliminating the need for additional layout space, thereby minimizing layout area and improving signal transmission efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transmission wires are extended to connect pads and memory blocks at long distances, then electrical coupling between pads and memory blocks is achieved, but layout area increases and parasitic resistance and capacitance increase
Solution Approach 1:
The patent employs asymmetric layout by positioning the pad disposing area at the center of the integrated circuit, allowing memory blocks to be arranged at different distances and orientations relative to the pads. This asymmetric configuration optimizes wire length for each memory block connection, reducing overall transmission wire area while maintaining reliable electrical coupling.
Solution Approach 2:
The patent transitions from conventional two-dimensional memory block arrangement to three-dimensional architecture, stacking memory blocks vertically above the pad disposing area. This dimensional change enables shorter transmission wire lengths by reducing the horizontal distance between pads and memory blocks, thereby decreasing layout area and parasitic effects.
2Reliability
If transmission wires are extended to connect pads and memory blocks, then electrical coupling is achieved, but parasitic resistance and capacitance increase reducing signal quality
Solution Approach 1:
By implementing three-dimensional memory block stacking, the patent reduces the horizontal transmission distance between pads and memory blocks. This dimensional transition significantly shortens wire length, thereby minimizing parasitic resistance and capacitance that would otherwise degrade signal quality over long transmission paths.
Solution Approach 2:
The patent divides the integrated circuit into multiple tiers with memory blocks stacked vertically, creating segmented connection paths. This segmentation allows signals to travel shorter vertical distances through dedicated interconnect layers rather than long horizontal paths, reducing cumulative parasitic effects on signal quality.
3Quantity of substance
If memory blocks are disposed at two sides of the integrated circuit, then memory capacity is increased, but transmission wire length increases requiring additional layout area
Solution Approach 1:
The patent resolves the contradiction between increasing memory capacity and reducing wire length by stacking multiple memory blocks vertically in three-dimensional tiers above the central pad disposing area. This vertical stacking enables high memory capacity without extending horizontal wire lengths, as all memory blocks connect to pads through short vertical interconnects rather than long horizontal traces.
Solution Approach 2:
The patent merges multiple memory blocks into a unified three-dimensional structure centered around the pad disposing area. By combining memory blocks from what would traditionally be separate lateral regions into a vertical stack, the design achieves high memory capacity while all blocks share common short-distance connection paths to the central pads, minimizing overall transmission wire length.
Data Source
AI summary
In one embodiment of this disclosure, an integrated circuit includes at least one first memory block, at least one second memory block, and a pad disposing area. The first memory block and the second memory block are respectively disposed at two sides of the integrated circuit, wherein each of the first memory block and the second memory block includes a memory cell array having a three-dimension structure. The first memory block and the second memory block are symmetrically disposed about the pad disposing area. A plurality of pads are disposed in the pad disposing area. The pads are respectively electrically coupled to the first memory block and the second memory block.