3D Memory Channel Bottleneck Structure for Critical Dimension Control
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Solution Overview
Problem
The integration limit of two-dimensional nonvolatile memory elements has been reached, necessitating the development of three-dimensional structures, which require improved reliability and manufacturing methods to maintain data integrity and efficiency.
Innovation Solution
A semiconductor device with a channel structure featuring a bottleneck pattern at the connection point of upper and lower channel structures, utilizing etch stop patterns to secure critical dimensions during manufacturing, including source layers, conductive patterns, and interlayer insulating layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional nonvolatile memory elements are used to increase integration, then manufacturing simplicity is maintained, but integration density reaches a limit
Solution Approach 1:
The patent transitions from two-dimensional memory element arrangement to three-dimensional structure by stacking multiple interlayer insulating layers and gate electrodes vertically. This dimensional change enables significantly higher integration density by utilizing the vertical space above the substrate, allowing memory cells to be arranged in multiple layers rather than a single plane.
2Quantity of substance
If three-dimensional memory structure is implemented to increase integration density, then integration limit is overcome, but manufacturing precision requirements increase
Solution Approach 1:
The patent incorporates etch stop patterns within the interlayer insulating layers before forming the channel structures. These etch stop patterns serve as predetermined reference markers that guide the etching process, ensuring that channel structures are formed at precise depths and positions. This preliminary action establishes critical dimensional references that simplify subsequent manufacturing steps and maintain tight tolerances.
Solution Approach 2:
The patent replaces direct mechanical control of etching depth with a chemical reference system using etch stop patterns. Instead of relying solely on mechanical positioning and depth control, the etch stop patterns provide a chemical/physical reference that automatically defines the etching termination point, thereby improving manufacturing precision for critical dimensions.
3Quantity of substance
If three-dimensional memory structure is implemented to increase integration density, then storage capacity is improved, but reliability maintenance becomes more difficult
Solution Approach 1:
The patent introduces etch stop patterns as intermediary structures within the three-dimensional memory architecture. These etch stop patterns serve multiple functions: they define precise boundaries for channel structure formation, provide reference planes for subsequent manufacturing steps, and ensure consistent positioning of critical components. This intermediary structure maintains manufacturing control and reliability despite the increased complexity of the three-dimensional configuration.
Data Source
AI summary
The present technology relates to a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a first source layer spaced apart from a substrate and overlapping with a cell region of the substrate, a second source layer spaced apart from the substrate and overlapping with a discharge contact region of the substrate, a cell stack including cell interlayer insulating layers and conductive patterns alternately stacked on the first source layer, and a channel structure passing through the cell stack and extending into the first source layer. The channel structure includes an upper channel structure passing through the cell stack and a lower channel structure extending into the first source layer, and a connection portion of the upper channel structure and the lower channel structure has a bottleneck pattern.