3D Memory Channel Connection Using Diffusion Layer and Metal Contact
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Solution Overview
Problem
In the manufacturing of three-dimensional memory semiconductor devices, connecting the interconnection layer with the channel semiconductor layer is challenging due to difficulties in the replacement process, particularly in forming memory holes and appropriately replacing sacrificial layers without damaging the channel semiconductor layers.
Innovation Solution
The semiconductor device manufacturing process involves bonding an array wafer to a circuit wafer, removing the substrate to expose channel semiconductor layers, and forming a diffusion layer and metal layer with higher impurity concentration to electrically connect with the channel semiconductor layers, thereby simplifying the connection process and avoiding the complexities of the replacement process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a sacrificial layer is replaced with an interconnection layer through a replacement process, then the memory cell can be connected with the source layer, but it becomes difficult to appropriately perform the replacement process without damaging the channel semiconductor layer
Solution Approach 1:
The patent forms the interconnection layer and source layer before forming the memory hole, rather than replacing a sacrificial layer after memory hole formation. This preliminary action allows the layers to be properly formed and connected without the risks of damage during replacement processes
Solution Approach 2:
The patent inverts the traditional sequence by forming the interconnection layer first and then forming the memory hole around it, rather than forming the memory hole first and then replacing a sacrificial layer with the interconnection layer. This inversion eliminates the replacement process and its associated risks
2Productivity
If memory holes are formed in traditional three-dimensional memory manufacturing, then the structure can be built, but the replacement process becomes complex and risky
Solution Approach 1:
The interconnection layer and source layer are formed preliminarily before memory hole formation, eliminating the need for subsequent replacement processes and reducing overall process complexity
Solution Approach 2:
The patent extracts and eliminates the sacrificial layer replacement step from the manufacturing process, directly forming the interconnection layer and source layer in their final positions, thereby simplifying the overall process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for easier formation of memory holes and source layers, ensuring appropriate connection to the channel semiconductor layers without the issues encountered in traditional replacement processes, enhancing the manufacturing efficiency and reliability of the semiconductor device.
Implementation Method 1
a second semiconductor layer including an impurity diffusion layer that is provided between the channel semiconductor layer and the source layer, electrically connects the channel semiconductor layer with the source layer, and has an impurity concentration higher than an impurity concentration of the channel semiconductor layer
Data Source
AI summary
In one embodiment, a semiconductor device includes a first substrate, and a plurality of electrode layers provided above the first substrate and stacked in a first direction. The device further includes a first semiconductor layer extending in the first direction in the plurality of electrode layers, and a metal layer provided above an uppermost one of the plurality of electrode layers and extending to cross the first direction. The device further includes a second semiconductor layer including an impurity diffusion layer that is provided between the first semiconductor layer and the metal layer, electrically connects the first semiconductor layer with the metal layer, and has an impurity concentration higher than an impurity concentration of the first semiconductor layer.