3D Memory Block Separation Structure for Channel Profile Control
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Solution Overview
Problem
As feature sizes of planar memory cells approach their limits, traditional fabrication techniques become challenging and costly, and controlling channel profiles in multi-layered 3D memory devices becomes increasingly difficult, limiting memory density.
Innovation Solution
The implementation of a semiconductor device with interleaved conductor and dielectric layers, separated by a dielectric stack, which allows for the formation of channel structures without the need for gate line slit structures, enabling more efficient word line replacement and reducing the device's size and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional planar fabrication techniques are used to scale memory cells to smaller sizes, then manufacturing precision is improved, but device complexity and fabrication cost increase significantly
Solution Approach 1:
The patent transitions from planar 2D memory cell architecture to three-dimensional stacked architecture with vertical channel structures extending through multiple memory decks. This dimensional change enables continued scaling of memory density without further reducing lateral feature sizes, thereby avoiding the fabrication complexity and cost increases associated with traditional planar scaling limits
2Quantity of substance
If the number of 3D memory layers is increased to improve memory density, then memory capacity is improved, but control of channel profiles becomes more difficult
Solution Approach 1:
The patent divides the continuous channel structure into discrete segments by introducing dielectric layers that partition the channel into separate sections between memory decks. This segmentation enables independent control and optimization of each channel segment, improving manufacturing precision for channel profiles even as the number of memory layers increases
Solution Approach 2:
The patent applies different dielectric materials with varying properties to different regions of the channel structure. Specifically, first dielectric layers are positioned at certain locations while second dielectric layers are positioned at other locations, allowing local optimization of electrical characteristics and channel control in different regions of the three-dimensional structure
3Adaptability or versatility
If gate line slit structures are used in 3D memory devices, then word line replacement is achieved, but device size and structural complexity increase
Solution Approach 1:
The patent removes the gate line slit structures entirely from the device architecture. Instead of using slits to achieve word line replacement, the invention employs a different mechanism where word lines are formed as continuous layers that can be selectively connected or disconnected through alternative structures, thereby eliminating the complexity associated with slit formation and registration
Data Source
AI summary
A semiconductor device includes a plurality of memory blocks. Each memory block includes a memory deck including interleaved first conductor layers and first dielectric layers, and a separation structure extending to separate two adjacent memory blocks. Each separation structure includes a dielectric stack including interleaved third dielectric layers and fourth dielectric layers. The third dielectric layers are in contact with the first dielectric layers, and the fourth dielectric layers are in contact with the first conductor layers.