3D Memory Channel Structure With CSP for Dense Chip-Scale Packaging
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Solution Overview
Problem
There is a need for high-capacity semiconductor memory devices with improved electrical characteristics and efficient integration of memory cells.
Innovation Solution
The integrated circuit semiconductor device includes a lower circuit pattern, bit line structure, gate electrode structure, and memory channel structure with a common source plate (CSP), featuring a staircase shape in the gate electrodes and insulation patterns to enhance integration and connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are 3-dimensionally stacked to increase data storage capacity, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent implements vertical stacking of memory cells in the third dimension (height direction) to increase storage capacity. Multiple memory cell layers are stacked above the substrate, with each layer containing memory cells formed over different regions. This dimensional transition from planar to vertical architecture enables higher density storage while managing complexity through systematic layering and standardized cell structures.
2Reliability
If gate electrode length is reduced to improve electrical characteristics, then electrical performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies different gate electrode lengths to different memory cell layers based on their specific electrical performance requirements. Upper memory cell layers have shorter gate electrodes compared to lower layers, optimizing electrical characteristics for each layer's operational context. This localized differentiation allows tailored electrical performance while using standardized manufacturing processes for each layer type.
3Quantity of substance
If memory cells are highly integrated to increase storage capacity, then data storage capacity is improved, but ease of manufacture decreases
Solution Approach 1:
The patent divides the memory device into multiple discrete memory cell layers, each containing a specific number of memory cells (e.g., 2, 4, 8 cells per layer). Each layer is manufactured as a separate unit with standardized structures, allowing modular fabrication and assembly. This segmentation enables high overall integration capacity while maintaining manageable manufacturing complexity through repetition of standardized layer patterns.
Data Source
AI summary
An integrated circuit device includes a lower circuit pattern on a substrate, a bit line on the lower circuit pattern, a gate electrode structure on the bit line, and a memory channel structure extending through the gate electrode structure. The memory channel structure includes a first capping pattern on the bit line, a channel on the first capping pattern, a second capping pattern on the channel, and a charge storage structure at outer sidewalls of the first capping pattern, the channel and the second capping pattern. A common source plate (CSP) is provided on the memory channel structure.