3D Memory Channel Doping After Wafer Bonding for Density Scaling
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Solution Overview
Problem
Planar memory cells face challenges in scaling beyond a certain limit due to costly and difficult fabrication processes, leading to density limitations.
Innovation Solution
A method for forming 3D NAND memory devices involves creating a stacked structure with alternating dielectric and conductor layers, forming channel structures, and bonding a CMOS wafer to an array wafer, with specific etching and deposition processes to achieve a stable and efficient 3D memory architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology and fabrication processes, then memory density is improved, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) stacked memory architecture. Multiple memory layers are stacked vertically, with each layer containing memory cells formed over different regions of the substrate. This vertical stacking enables continued memory density scaling without requiring further reduction of lateral feature sizes, thereby avoiding the manufacturing complexity and cost increases associated with extreme planar scaling.
2Quantity of substance
If planar memory cells are scaled to smaller sizes, then memory density is improved, but manufacturing cost increases
Solution Approach 1:
By stacking multiple memory layers vertically, the patent achieves higher memory density without requiring proportionally higher manufacturing costs. The shared substrate and common fabrication processes across layers provide cost efficiency compared to continuing to scale planar cells to extremely small dimensions, which would require increasingly expensive and complex manufacturing techniques.
3Quantity of substance
If planar memory cells are scaled to smaller sizes, then memory density is improved, but fabrication difficulty increases
Solution Approach 1:
The 3D stacked architecture allows memory density scaling through vertical layering rather than lateral shrinking. This approach uses standard fabrication processes repeated across multiple layers, avoiding the fabrication difficulty and process challenges that arise when attempting to manufacture planar memory cells at extremely small feature sizes.
Data Source
AI summary
A method for forming a 3D memory device is provided. The method comprises forming an array wafer including a core array region, a staircase region, and a periphery region. Forming the array wafer includes forming an alternating dielectric stack on a first substrate, forming a plurality of channel structures in the alternating dielectric stack in the core array region, each channel structure including a functional layer and a channel layer, forming a staircase structure in the staircase region, and forming a plurality of dummy channel structures. The method further comprises bonding a CMOS wafer to the array wafer; and removing the first substrate; removing a portion of functional layer of each channel structure to expose channel layer, and doping the exposed portion of the channel layer.