3D Memory Channel Doping for Conductivity and Complexity Trade-off
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Solution Overview
Problem
Current three-dimensional memory structures, such as vertical NAND strings, face challenges in achieving optimal conductivity and doping profiles, which affect the performance and efficiency of memory devices.
Innovation Solution
A monolithic three-dimensional memory structure is developed, comprising a stack of alternating insulator and conductive layers over a substrate with a memory opening, featuring a semiconductor channel with intrinsic and doped portions, and strategically positioned drain regions, along with a method of manufacturing that involves forming backside recesses and introducing electrical dopants to optimize conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniform doping is applied throughout the semiconductor channel, then manufacturing process is simple, but conductivity and performance are suboptimal
Solution Approach 1:
The patent applies local quality by creating distinct doping regions within the semiconductor channel. The channel is divided into a first portion with first doping concentration and a second portion with second doping concentration, allowing each region to have optimized electrical properties for its specific function in the memory device operation.
Solution Approach 2:
The semiconductor channel is segmented into multiple portions with different doping characteristics. This segmentation enables independent optimization of conductivity in different regions, improving overall device performance while managing the complexity through structured differentiation.
2Reliability
If selective doping regions are created in the semiconductor channel, then conductivity and performance are optimized, but manufacturing process complexity increases
Solution Approach 1:
The patent employs preliminary action by forming the doping profile during the semiconductor channel formation process itself, rather than requiring separate post-processing steps. The selective doping is integrated into the channel creation sequence, which simplifies the overall manufacturing flow despite the increased doping complexity.
3Device complexity
If drain region is positioned at upper end of semiconductor channel, then device structure is simple, but conductivity control is limited
Solution Approach 1:
The drain region is positioned to contact the second portion of the semiconductor channel, creating a localized high-conductivity region at the interface. This local quality enhancement allows for better conductivity control in the drain area without significantly complicating the overall device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the conductivity and doping profiles, improving the performance and efficiency of three-dimensional memory devices by optimizing the semiconductor channel and drain region placement.
Implementation Method 1
Electrical dopants are introduced through each physically exposed portion of the outer sidewall of the semiconductor channel and into each respective adjoining portion of the semiconductor channel, which is converted into a doped semiconductor channel portion
Data Source
AI summary
A stack of material layers includes first material layers, second material layers located between a respective pair of an overlying first material layer and an underlying first material layer, and at least one temporary material layer located between a respective pair of an overlying first material layer and an underlying first material layer. After formation of a memory opening and a memory stack structure, at least one first backside recess is formed by removing the at least one temporary material layer and adjoining portions of a memory film. A physically exposed portion of a semiconductor channel is doped with electrical dopants to form a doped semiconductor channel portion. Second backside cavities are formed by removal of the second material layers. The backside cavities are then filled with a dielectric liner and electrically conductive layers, such as select and control gate electrodes of a memory device.