3D Memory Channel Hole Uniformity via Sacrificial Holes
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Solution Overview
Problem
Three-dimensional (3D) NAND flash memory devices face challenges in forming channel holes with uniform dimensions due to variations in pattern density, leading to impaired device performance and non-uniformity issues.
Innovation Solution
The method involves forming sacrificial holes adjacent to channel holes with the same dimensions, allowing for uniform etching conditions and improved dimensional uniformity, and subsequent replacement with dielectric filling structures to facilitate the formation of gate line slits and conductive materials, thereby enhancing the fabrication process and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If channel holes are formed by patterning/etching process, then channel holes can be created in the material layer, but dimensional uniformity deteriorates due to pattern density variations
Solution Approach 1:
Sacrificial holes are introduced as intermediary structures surrounding the channel-forming holes. These sacrificial holes act as mediators that modify the local pattern density environment, providing a buffering effect that compensates for density variations and enables more uniform etching conditions across different regions of the array.
Solution Approach 2:
The invention changes the physical parameters of the etching environment by introducing sacrificial holes with specific dimensions and arrangements. By controlling the number, size, and distribution of sacrificial holes, the local pattern density parameter is modified to achieve consistent etching rates and dimensional uniformity in the channel holes.
2Manufacturing precision
If sacrificial holes are formed around channel holes, then etching uniformity improves, but fabrication process complexity increases
Solution Approach 1:
The formation of sacrificial holes and channel holes is merged into a single patterning and etching step. Both types of holes are created simultaneously through one photoresist application and one etching process, eliminating the need for separate fabrication steps and reducing overall process complexity despite the additional structural element.
Solution Approach 2:
The sacrificial holes serve multiple functions: they act as etching uniformity buffers, define array boundaries, and provide structural support during subsequent processing steps. This multi-functionality justifies the additional structures by delivering multiple benefits from a single added element type.
3Productivity
If channel holes are formed in array-forming region, then device integration is achieved, but dimensional deviations occur due to edge effects
Solution Approach 1:
The array-forming region is segmented into internal channel-forming holes and boundary sacrificial holes. This segmentation allows the edge effects to be isolated to the sacrificial hole regions, protecting the internal channel holes from dimensional deviations caused by boundary conditions and enabling consistent dimensions across the integrated array.
Data Source
AI summary
A method for forming a three-dimensional memory device includes disposing a material layer over a substrate, forming a plurality of channel-forming holes and a plurality of sacrificial holes around the plurality of channel-forming holes in an array-forming region of the material layer, and forming a plurality of semiconductor channels based on the channel-forming holes and at least one gate line slit (GLS) based on at least one of the plurality of sacrificial holes. A location of the at least one GLS overlaps with the at least one of the plurality of sacrificial holes.