3D Vertical Channel Memory Structure for Lower-Cost Integration
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Solution Overview
Problem
Existing two-dimensional or planar semiconductor devices face limitations in integration due to the expensive equipment required for fine pattern formation, which restricts the increase in data storage capacity needed for advanced electronic systems.
Innovation Solution
A nonvolatile three-dimensional semiconductor device with a vertical channel structure is developed, featuring a substrate with a recess region, a gate electrode, shield electrodes, and dielectric patterns, which enhances electrical properties and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional or planar semiconductor devices are highly integrated to increase data storage capacity, then integration density improves, but manufacturing cost increases due to expensive processing equipment required for fine pattern formation
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked devices. By stacking multiple memory cell layers vertically, the device achieves higher integration density and data storage capacity without requiring finer lateral patterns, thus avoiding the need for expensive fine pattern processing equipment
2Manufacturing precision
If fine pattern formation is used to increase integration of two-dimensional semiconductor devices, then integration density improves, but manufacturing complexity increases due to expensive processing equipment
Solution Approach 1:
The invention forms memory cells in three dimensions with vertical stacking, allowing integration density to be increased through the vertical dimension rather than through lateral pattern refinement. This approach avoids the need for complex fine pattern formation processing equipment
Solution Approach 2:
The three-dimensional memory device is divided into multiple stacked memory cell layers, each layer being relatively simple in structure. This segmentation allows each layer to be formed using standard processing techniques without requiring advanced fine pattern formation equipment
Data Source
AI summary
Disclosed are semiconductor devices and electronic systems including the same. The semiconductor device includes a substrate that has a recess region, a gate electrode on a bottom surface of the recess region, a gate dielectric layer between the gate electrode and the bottom surface of the recess region, a plurality of shield electrodes on laterally opposite sides of the gate electrode and on inner sidewalls of the recess region, a plurality of dielectric patterns between the shield electrodes and the inner sidewalls of the recess region, a plurality of impurity regions in the substrate and on opposite sides of the shield electrodes, and a channel region in the substrate and below the bottom surface of the recess region.